SupportBlog Posts
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Your problem is not AXI
This is response to a student's question about not being able to get an AXI slave to work. Sometimes the problem is simply more fundamental.
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My Personal Journey in Verification
I've now gone from hardware-only verification, to simulation, through formal verification, to automated test suites. This article attempts to discuss why I've used all these steps together with some of the lessons learned along the way.
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Debugging video from across the ocean
Two years ago, I built and verified several data display modules. They passed simulation, and looked great on my screen. Now, only two years later, I've finally been able to discover why the waterfall display didn't work in hardware kept on the other side of the Atlantic Ocean.
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Bringing up Kimos
Hardware is hard. Even the simplest of bugs takes time. Let's talk about the Kimos project today, and the challenge to get the DDR3 SDRAM up and running.
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Chasing resets
A true story of a design, delivered late, due to (several) unexpected problems.
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2023, Year in review
Let's look back over 2023 from the standpoint of the ZipCPU blog, and Gisselquist Technology's business
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An Overview of a 10Gb Ethernet Switch
Our 10Gb Ethernet Switch is an open design, from the RTL to the PCB the FPGA is hosted on. This article presents an overview of the networking handling within the router, what components form that path, and a quick introduction to how the routing works within the switch.
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SDIO RX: Bugs found w/ Formal methods
My SDIO controller has now been tested, successfully, via simulation with success. It builds on hardware. What value, therefore, is left for formally verifying it? Let's therefore examine and count the number of bugs found while formally verifying the receive portion of this controller.
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Using a Verilog task to simulate a packet generator for an SDIO controller
This article tells the story of the ongoing development of an SDIO controller, paying particular attention to how a Verilog task can be used to generate data to test one part of that controller.
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Introducing the ZipCPU v3.0
It's time to announce a new version of the ZipCPU: ZipCPU v3.0! This article discusses the differences between this version of the ZipCPU and prior versions.
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What is a Virtual Packet FIFO?
We know what FIFOs are, but what's a virtual packet FIFO?
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What is a SwiC?
Central to the motivation behind the ZipCPU is the concept of a System within a Chip, or SwiC. Let's look at what defines a SwiC, and see how that applies to the ZipCPU.
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Debugging the Hard Stuff
Some digital design spaces are just really hard to debug: ECC, FFTs, and cryptography are good examples of these. Let's look at some ways faults in these types of designs can be isolated.
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Your soft-core CPU won't boot. Where should you start debugging?
Let's look into several things you can do in order to find and diagnose boot failures on a soft-core CPU.
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Thanksgiving! I have much to be thankful for
This thanksgiving, I have much to be thankful for. The greatest among these are my salvation, family, and business.
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Quiz #23: Can this assertion fail?
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A first lesson in sales pitches: Honesty
Since my spam box seems to be filled with offers to redesign my web site, I thought I might take a moment to respond to these requests.
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Quiz #22: Handling cover failures
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Measuring the Steps to Design Checkoff
Before delivering a design to a customer, it's important to have a strong confidence it will work. Prior to that time, it's important to know how much time and work remain in the project. In this article, I'll demonstrate a tool I've now used with great success for that purpose.
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Assignment delay's and Verilog's wait statement
I'm now spent more time than I want to admit to debugging simulation issues when using Verilog's simulation semantics. This article is an attempt to capture the lessons I've learned along the way.
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It's not my fault! Your code is broken.
Getting verification right is not a simple task. It takes patience and hard, methodical work.
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Protocol Design for Network Debugging
TCP can be a challenge in an FPGA. What shall be done when you need TCP's reliability, but can't afford the logic required?
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Quiz #21: Verifying all configurations of a design
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ZipCPU Lesson: If it's not tested, it doesn't work.
A single test is often not sufficient to fully test a complex and highly configurable design. Let's look a how a flexible script can help test multiple configurations of the ZipCPU.
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A Coming Economic Downturn? or Worse?
Every economist I read is discussing the impending disaster. Today, let's discuss how to prepare.
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Quiz #20: Using $stable in a multiclock environment
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Learning AXI: Where to start?
The AXI specification is the wrong place to start learning AXI. Here's a list of some ZipCPU articles that'll help you get started.
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Bringing up a new piece of hardware -- what can go wrong?
This last week was the first time we fired up our SONAR system. How do you think it went?
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Rethinking Video with AXI video streams
My original video work has seen a revitalization with AXI Stream
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AXI Stream is broken
Few AXI stream sources can truly handle backpressure. Here I offer a solution for network packet data, via a packet ABORT signal.
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2020 and 2021 in review
In honour of the new year, let's take a look back at the last two years and highlight the best posts from among them.
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Quiz #19: Using disable iff in a concurrent assertion
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Creating a Simple AXI-Lite Master for the Hexbus
While much of my recent AXI work has focused on building bursting AXI masters, the debugging AXI-lite master makes a nice example of how simple an AXI master can be.
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Envisioning the Ultimate I2C Controller
Just a quick thought regarding the design of what I consider will be an ultimate I2C controller
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Clock Gating
Can clock gating be used to improve simulation performance? Let's take a look.
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Upgrading the ZipCPU's memory unit from AXI4-lite to AXI4
AXI4 offers an opportunity for exclusive access and bursting capabilities not present in AXI4-lite. Let's look at the changes, therefore, made to the ZipCPU's memory controller to upgrade it from AXI4-lite to AXI4.
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Quiz #18: Failures in clocked immediate assertions
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AXI Handshaking Rules
Let's look at some simple AXI handshaking rules for success, follow them up with example templates showing how to following them and then how to verify the rules are followed. We'll also look at some broken example designs along the way to see examples of what can go wrong.
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Measuring AXI latency and throughput performance
It's important when using any tool to know how well it performs. This article discusses how to measure the performance of any link in an AXI system.
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Quiz #17: Induction failures
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The other half of the Gospel
The other half of the Gospel is healing. Jesus healed men then. He still heals men today.
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CPU based simulation, first thoughts
When testing, something needs to drive your test--a script of some type. This article explores the question of whether or not that script should be written in software to run on a soft-core CPU, or in Verilog/VHDL?
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Quiz #16: Immediate assertions in the presence of asynchronous resets
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Building a Better Verilog Multiply for the ZipCPU
Low logic and soft multiplies don't often go together. Here we discuss how to create a slow multiply in hardware, using a minimum amount of logic, for the case where no hardware accelerators are available.
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Examples of AXI4 bus masters
At user request, here's a list of AXI4 master's I've recently built, and two of the test beds I've been using to test them.
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Quiz #15: Pass-through memory
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Fixing Xilinx's Broken AXI-lite Design in VHDL
While I don't normally do VHDL work, I recently had the opportunity to verify Xilinx's AXI-lite demonstration design (again)--this time in VHDL. So I thought I'd write about it, and offer some quick and easy fixes to the design along the way.
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Building a Simple AXI-lite Memory Controller
When building a CPU memory controller, I like to start with the simplest memory controller that will do the task. Here is a very basic AXI-lite memory controller for the ZipCPU.
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Common AXI Themes on Xilinx's Forum
Let's take a quick look through Xilinx's forums, to see if there are some common AXI themes among the forum help requests.
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Whatever happened to the ZipOS?
The ZipOS was used early on with the ZipCPU in the S6SoC project, and then we haven't heard of it again since. What happened to it?
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Lessons learned while building an ASIC design
With a background in FPGA design, I was asked to try my skill in an ASIC design. Here are some things I learned.
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The FPGA designer who didn't get the job
Lots of people will claim an ability in digital logic design these days. Finding someone with character, someone who will be easy to work with who also has that ability isn't nearly as easy.
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Ultimate Logic
Logic can be used to prove that certain assertions must follow from the given assumptions. How then shall the assumptions be validated? What about the assumptions behind the assumptions?
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Quiz #14: Two nearly identical frequencies
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Formally verifying register handling
We've already discussed how to build a peripheral, and to verify its bus interaction. Let's now look at how to verify the register contents.
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Is it possible to make a living as a solo digital design engineer?
For Thanksgiving this year, let me share a bit of the story about how Gisselquist Technology came to be.
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Spectrograms need Window Functions
Let's examine the basics of localizing signal energy in time and frequency bins, showing from first principles the need for a window function how overlap choice affects this choice of taper. We'll then look at how to implement a window function in both C++ and Verilog.
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A fun Friday evening--verifying an AXI-lite slave
Can an AXI-lite slave design be formally verified, from scratch, while others look on?
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Moving values and strobes cross clock domains
Let's build a two-phase clock-domain crossing algorithm to move words from one domain to another, beating our prior four-phase method in performance and logic.
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Quiz #13: Temporal assertion equivalences
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Run length encoding an AXI stream
Run length encoding makes a nice complement to any logic analyzer. Let's take a look at how to build and verify a run-length encoder in Verilog.
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Driving an output on both edges of the clock
Every now and then you need a replacement for a library element. Today, we look at generating an ODDR output component to output logic on both edges of the clock.
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Building a Downsampling Filter
A digital downsampler is a combination of both a digital filter and an every Nth element selector. It's basic. Formally verifying it, perhaps not quite so basic.
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I have a brand new piece of IP. How shall I verify it?
Verification doesn't begin once a design is complete. It needs to begin long before that, ideally before the design is ever simulated in the first place
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Measuring clock speed
A counter makes a very simple means of measuring clock speed. Let's take a look at how to do that.
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The hard part of building a bursting AXI Master
Getting an AXI master to generate high throughput burst requests involves some challenging criteria which can compete with a high clock speed.
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Four keys to getting your design to work the first time
No, it's not a magical cure, just a general observation: there are four key pieces to verification that come back over and over again in designs that just work the first time
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Quiz #12: Catching extraneous acknowledgments
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Building a Protocol Firewall
A bus fault isolator can be a very useful tool for debugging an AXI interaction within an active design. Once the bus faults and the design locks up, further debugging is a challenge. However, if a fault isolator can keep things from locking up and perhaps even reset the quarrelsome component following a fault, then finding the bug gets a lot easier.
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Debugging AXI Streams
Debugging a broken AXI stream is a common problem appearing over and over again on various forums. In-Circuit Logic Analyzers don't do the problem justice, and often instead hide critical details of the stream protocol. In this article, we'll look at how to build a key piece of scaffolding you might use to debug an AXI stream processor.
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Adding an AXI-Lite interface to your Verilator test script
There are lots of ways to test AXI components, my favorite being formal methods. Every now and again, though, you need a simulation where you can script AXI interactions. This article explores how to do that from a C++ Verilator test bench--something that can be used to (nearly) simulate an on-board CPU.
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Re: What does your design flow look like?
Someone recently asked me if I had a post or something that described the tool chain I used for my own development. This article walks through my preferred tools, and how or when I might use them. It also contains several examples of lessons learned along the way.
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Building a basic AXI Master
A bridge from Wisbone to AXI makes a marvelous example of how one might build an AXI master
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Cheap Spectral Estimation
Placing an FFT inside an FPGA just to debug what may be going right or wrong with your DSP algorithm can be a costly addition. Let's look instead at an AutoCorrelation based alternative which can get us to roughly the same result, while moving the difficult math out of the real-time flow and into a nearby processor.
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Locally resetting an AXI component
It's often advantageous to bring a single component within a design back to a known reset state. Doing this without impacting the other items within the design can be a challenge. Here, we'll look at examples of resetting both an AXI slave and an AXI master without resetting the rest of the surrounding design.
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Adjusting our logic PLL to handle I&Q
By making some simple changes to the phase estimator of our logic PLL, it can be made to run in a quadrature I+Q context
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Buidilng an AXI-Lite slave the easy way
After building several AXI-Lite slave interfaces, they've become almost routine and easy to build. In this article, we examine how easy and simple a fully functional AXI-Lite slave interface can be to build.
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The Faith of a Mustard Seed
Whether or not a man has faith as a grain of mustard seed was never about the size, quantity, or amount of his faith. If you look at what a mustard seed does, you'll realize that a mustard seed is an amazing example of what faith is in the first place.
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A Histogram Gone Bad
I took my working histogram component, and placed it into a full design. It didn't work. Let's take a look at what happened.
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Quiz #11: Induction and clock enables
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Quiz #10: Checking stall conditions
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Lessons in Hardware Reuse
Hardware component reuse has been a goal of digital designers for a long time. Let's look at some lessons learned regarding hardware reuse within a company, where reuse should be easy.
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2019: AXI Meets Formal Verification
This article looks over 2019 in review from the perspective of the ZipCPU blog. In particular, the top ZipCPU blog articles across all of 2019 are reviewed.
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The Christmas Gospel
Let's trace the origins of Christmas, from beginning to end
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Using a Histogram to Debug A/D Data Streams
Histograms are an important part of debugging a data channel. Let's take a look at some pictures, and then discuss how to go about implementing one
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Quiz #9: Immediate assertions midst blocking assignments
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Quiz #8: Will this pass a bounded model check?
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The ZipCPU meets blinky
FPGAs and CPUs blink lights in very different manners. The difference? CPUs have interrupts, and contexts which can be swapped. Let's take a look and see how these might be used on a ZipCPU.
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Formally Verifying a General Purpose Ultra-Micro Controller
Let's look at a basic, scripted microcontroller--the simplest around. Understanding how to formally verify something this simple offers a lot of lessons for verifying something more complex.
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Quiz #7: Returning to $past() and our counter again
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Putting the pieces together to build a data recorder
We've discussed building components before. Today let's look at a (much too long) journey from components to completed design.
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Is formal verfication enough, or is simulation required?
This article captures four stories I tell of bugs found and caught, two after only using simulation and two after only using formal, in an attempt to answer whether or not I could've verified with formal alone or for that matter with simulation alone.
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Quiz #6: Synchronous logic in Asynchronous contexts
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AXI Verification, the story so far
After learning how to verify AXI modules, it's now time to discuss some of the reality of what's going on in the industry.
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Understanding AutoFPGA's address assignment algorithm
Address assignment is often seen as a black box to many folk. It need not be. The algorithm used by AutoFPGA isn't that hard to understand or follow. This article describes how that algorithm works.
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Quiz #5: Immediate vs Concurrent Assertions
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Connecting lots of slaves to a bus without using a lot of logic
AutoFPGA has long supported classes of slaves using a simplified bus protocol. Today, we'll examine what that would look like for WB, AXI-lite, and AXI.
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Quiz #4: If this counter is never triggered, can we prove it'll never leave zero?
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Technology Debt and AutoFPGA, the bill just came due
Knowing how the interconnect works, I've abused the Wishbone protocol several times. Now that I'm updating AutoFPGA to handle multiple masters, making them work with the updated bus interconnect requires fixing what only appeared to be working before.
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Xilinx deleted this post
Some hard wisdom I've learned about learning hardware design--wisdom that Xilinx deleted because it doesn't flatter them.
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Quiz #3: Will formal verification prove this counter keeps its bounds?
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Planning an Intermediate Design Tutorial
My first Verilog+Formal tutorial has been well received. Today, I put some thoughts together about where I might take the tutorial next. Specifically, what should the next lesson(s) be?
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Quiz #2: Will this counter pass formal verification?
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Quiz #1: Will the assertion below ever fail?
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Just how long does a formal proof take to finish?
Formal methods are exhaustive, so just how long does it take to prove something? Examining a body of nearly 900 proofs, it's not that long.
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Lessons learned while building crossbar interconnects
Connecting N bus masters to M bus slaves is the task of an interconnect. While many approaches exist, one of the most common FPGA approaches is a crossbar interconnect. This article examines some common features among several crossbar interconnects I've recently built.
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Breaking all the rules to create an arbitrary clock signal
Never generate a clock signal using logic! Why not? Let's break this rule today in order to create an arbitrary clock generator and see how things work out for us.
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Building the perfect AXI4 slave
Xilinx provides example code which can be used to build an AXI slave from. As we've already seen, this code is broken to the extent that it can be made to violate the AXI protocol. Worse, even when it does work the demo core does not perform well. Here's an example of how to do better.
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Building a Skid Buffer for AXI processing
Skid buffers provide an elastic support between pipeline stages, relieving the pressure from combinatorial logic which would otherwise accumulate from one stage to the next.
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Examining Xilinx's AXI demonstration core
Vivado has a wonderful capability, whereby it can create a AXI4 IP core for you to build a design off of. Sadly, the core generated by Vivado 2018.3 doesn't pass formal verification. Let's look at some of the problems with it today.
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Understanding AXI Addressing
An AXI4 component must three different addressing modes, 8 different sub-word sizes, four different wrapping lengths, and both aligned and to-be-aligned addressing. It's not trivial. This article takes a look at how you can compute the next address in an AXI burst.
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Project Ideas: PMod AMP2
Do you have a PMod AMP2? Are you wondering what to do with it? Here are some ideas
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Applying Formal Methods to the Events of the Resurrection
When was the last supper? When was the crucifixion? Friday? How about the sabbath? Let's apply formal methods to discover these events
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The most common AXI mistake
After formally verifying several AXI-lite slaves, one bug stands head and shoulders above the rest as the most common bug
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The ZipCPU's Interrupt Controller
The ZipCPU has only a single interrupt line. For many microprocessor applications, this is way too few. Therefore, let's discuss how to build a simple interrupt control peripheral that can then give the ZipCPU access to more than just the one interrupt
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Logic usage and decoding return results with cascaded multiplexers
How your CPU or bus aggregates return values from its components, can have an affect on your logic usage
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Building a universal QSPI flash controller
In this article, I'll discuss how to build a QSPI flash controller in Verilog, and then make sure it works under all configurations. As always, formally verified example code is provided.
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Introducing the ArrowZip ZipCPU design, featuring the Max-1000
The Max-1000 is a very small and cheap FPGA development board from Trenz, and sold by Arrow in the US for only $30. Today, let's take a an example design that runs the ZipCPU on this board.
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Using Sequence Properties to Verify a Serial Port Transmitter
Formally Verifying a serial port makes a great example of both the good and bad about SystemVerilog sequences, and how you can still work around the bad with SymbiYosys
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Why does blinky make a CPU appear to be so slow?
If your CPU runs at 100MHz, what speed would you expect it to be able to blink an I/O pin at? Let's take a look.
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Debugging a CPU
This is the story of finding and fixing a bug in the ZipCPU. As with most bugs, the bug I found wasn't where I expected it. Along the way, though, we'll go over several tools you can use to accomplish such a task--should you ever find you need to do so yourself.
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Building a custom yet functional AXI-lite slave
Some time ago, I wrote on this blog about how to verify an AXI-lite slave, showing along the way how Xilinx's demonstration slave wouldn't pass a verification test. Instead of illustrating the problem again, let's take a moment to examine how to build an AXI-lite slave that will not only work, but have twice the throughput.
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ZipCPU highlights from 2018
A quick summary of the highlights of the ZipCPU blog over 2018, to include a list of the most read articles
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Using a formal property file to verify an AXI-lite peripheral
A file of formal properties defining an interface is worth gold: you can get a strong guarantee that your code will conform to the interface if it passes a formal verification step using the interface. Even better, one such file, used across an enterprise, can guarantee that all of the cores within the enterprise are interface compatible.
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AutoFPGA's linker script support gets an update
AutoFPGA is a very powerful scripting tool for composing ad-hoc System on a Chip (SoC) designs. Today it gets an update for handling linker scripts.
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Makefiles for formal proofs with SymbiYosys
Building a make script to verify multiple configuration options using SymbiYosys can be done very easily. Let's take a quick look and see how that might be done.
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Swapping assumptions and assertions doesn't work
Some time ago, I blogged about how to go about aggregating subcomponents together into a larger design. While I've used the technique often with great success, this article shares a counter example that renders the approach invalid.
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Building a video controller: it's just a pair of counters
Building a video display can be a fun beginners exercise: at its fundamental core, it just consists of a pair of counters. This article will examine the lower level component of a video display controller for a VGA display.
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Accessing the registers of a SoC+FPGA
Accessing the memory mapped registers connected to a CPU-attached FPGA is usually easy to do. However, if you are doing this from within a Linux system, across a virtual memory interface, then there are a couple more steps involved. The result is still fairly simple.
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Taking a look at the TinyFPGA BX
The TinyFPGA BX offers a new approach to the classic FPGA loading problem. Let's take a look at this board and see what it offers.
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To my new readers and my new twitter followers, welcome!
I've recently acquired several new twitter and blog feed followers. Today, I'd like to take a moment to welcome them, and let them know what they can expect from the ZipCPU blog.
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An Open Source Pipelined FFT Generator
Not having an open source FFT implementation can make simulating DSP algorithms with an open source simulator such as Verilator nearly impossible. Now there's a highly configurable open source alternative. Better yet, this alternative has been formally verified. We'll discuss that FFT, and how the formal verification was accomplished, here.
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It's time for ORCONF 2018!
ORCONF 2018 will be held this weekend in Gdansk, Poland. I look forward to meeting many of you there. Here's the abstract of what I intend to present this year.
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My design works in simulation, but not in hardware. Can formal methods help me?
Formal methods are traditionally viewed as a design tool to be used before implementation. Today, let's take a peek at a recent example where formal methods were able to help me after implementation.
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Handling multiple clocks with Verilator
If you look through the Verilator on-line documentation, you'll notice that all of the examples use a single clock only. Verilator is more capable than that, so let's try to fill in that gap today. This article takes a quick look at how you might handle multiple clocks within Verilator.
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RE: Building a simulation for my design? What does that mean?
A student recently asked me what I meant by simulating a design. To answer his question and encourage others, let's spend a moment and look at some examples of what you can do with simulation. I'll also offer several links to other blog posts showing you how to do many of these things.
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How to build a SPI Flash Controller for an FPGA
I've now written several (Q/D)SPI flash drivers, and just recently had the opportunity to build another. Here I present the design decisions, the design, and even the formal verification of this new core.
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Reasons why Synthesis might not match Simulation
I now recommend simulation to anyone doing HDL design. It's can even be faster to run and debug a simulation then actual hardware. However, there are plenty of times when simulation doesn't match reality. Let's enumerate some of the reasons why simulation might not match hardware performance.
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Why I like Formal: the ZipCPU and the ICO board
Recently, I had to move logic from one clock to another in order to fit the ZipCPU onto the ICO board. Having a set of formal properties for the ZipCPU, properties that covered this change, gave me a strong confidence when making the change that the result would still work.
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What does Formal Development look like in Practice?
I just built a basic, simple SPI controller last night, using formal tools along the way. Care to read what the development was like?
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Formally Verifying Memory and Cache Components
There's a necessary but basic trick necessary when formally verifying something that acts like or interacts with memory, and it's not all that hard to do. In this article, I'll present that basic trick and show how to formally verify a block RAM device.
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Crossing clock domains with an Asynchronous FIFO
A two or three clock synchronizer works great for passing small amounts of information across clock domains. If you need to pass more information, such as a full data stream, you will need an asynchronous FIFO. This article examines the Asynchronous FIFO designed by Cliff Cummings, applying formal methods to it to see if it truly maintains the properties he discusses.
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Formally Verifying Asynchronous Components
There's a very small bit of trickery required to formally verify an asynchronous design using yosys. Once you know the trick, it becomes easy to set up the properties necessary to formally verify any asynchronous design. In this article, we'll demonstrate this principle by formally verifying a clock switch.
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A Slow but Symmetric FIR Filter Implementation
The cost of an FIR filter is usually measured by the number of multiplies required to calculate an output. If you want to implement a better filter, you only need to be able to afford more multiplies. However, if the filter is symmetric, and most FIR filters are, then a little cleverness will allow you to implement the same filter with half as many multiplies.
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Updated Projects List
Just a quick note to let everyone know I updated my projects page.
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Aggregating verified modules together
Aggregating multiple modules together to formally verify a larger whole can be a very difficult challenge. While I am by no means the expert on this topic, I can at least share some lessons I've learned myself.
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ZipTimer: A simple countdown timer
When learning Formal Verification, it helps to start with the simplest designs possible. The ZipTimer is just about that simple: it is nothing more than a programmable countdown timer. More than that, though, it's a usable and critical component of the ZipSystem. Today, let's examine that timer and then formally verify it.
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Formally Verifying an Asynchronous Reset
It's one thing to synchronize reset logic within your code, its another to formally prove that your reset synchronizing logic works. This article takes a look at an example reset synchronizer, and then applies SymbiYosys to formally verifying that it works.
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What would you like to see on the ZipCPU blog?
It seems there are more topics to post about then there is time to post or to read them. Hence, it's time to ask my Patreon sponsors what topics they'd be interested in reading about next, and thus where my focus should be for the next couple of months. If you are not a blog sponsor, please consider yourself invited to become one!
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Will formal methods ever find a bug in a working CPU?
I've now turned my attention to formally Verifying the ZipCPU. Having used the ZipCPU for several years, do you think I'll find any errors within i?
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Resurrection Day!
Today is the day Christianity celebrates the resurrection of Jesus Christ. Please join me in reflecting on what makes Jesus different.
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Quadratic fits are entirely inappropriate for DSP
If you ever need to estimate a signal's value between samples points, don't use a quadratic fit. There are much better techniques out there which don't suffer from the discontinuities and high frequency distortions associated with a simple quadratic fit. Want to see an example?
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Pipelining a Prefetch
We've already discussed the simplest of the ZipCPU's several prefetch modules. Today's discussion focuses on another module that's nearly as simple, but yet can achieve much better performance.
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Is formal really all that hard?
There seems to be a myth that formal verification is very difficult, and that it is only used by the smartest digital designers. Let me take a moment in this article to dispel that myth: If you are smart enough to do digital design, then you will appreciate the benefits of formal verification
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An Exercise in using Formal Induction
Passing N steps of a formal bounded model check isn't nearly as hard as proving a design works for all steps. This post explores some of the differences, and offers some explanations for those new to formal methods.
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Want to use ZBasic? Let's have some fun--no actual FPGA required!
The ZBasic distribution is a very basic ZipCPU distribution that has full Verilator support for all of its peripherals: flash, serial port, and an (optional) SD-card. Want to play a game?
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Debugging a Cyclone-V
I just delivered my first design using the Cyclone-V. It was a new experience for me, and I'd like to share some lessons learned in debugging.
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ZipCPU toolchain and initial test
This article discusses how to clone the ZipCPU repository from github, and then build the compiler and toolchain. The toolchain is then proven using the basic simulation test program that comes with the ZipCPU repository.
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Updating ZipCPU files
I'll admit, I've enjoyed formal methods so much I've started formally verifying much of the ZipCPU repository. Here's a quick status update of what's been accomplished.
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Interpolation is just a special type of convolution
One of the more profound DSP lessons I ever learned was that most practical interpolators can be understood as convolutions. This is important because it means that interpolation function have frequency responses, and that their performance can be understood by examining this response.
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A Quick Introduction to the ZipCPU Instruction Set
If you've ever wanted to examine a minimalist, yet still powerful, CPU's instruction set, then you might wish to take a peek at the ZipCPU's ISA. If you've ever wanted to program the ZipCPU in assembly, or evaluate or understand an assembly representation of a ZipCPU program, then read along and see the basics of the ZipCPU instruction set.
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Top 10 ZipCPU blog posts for 2017
In the spirit of all good New Year's blog posts, here's a quick list of the top ten blog posts on ZipCPU.com from this last year.
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A better filter implementation for slower signals
All of the filter implementations we've presented so far are high speed implementations--appropriate for signals at or close to the system clock rate. These implementations, however, end up being very resource expensive when all you want to do is to filter a much slower signal--such as an audio signal. This post, therefore, presents an alternative that is more resource efficient for audio signals.
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Mystery post: The ugliest bug I've ever encountered
For someone who has been debugging software for many years, this bug caught me by surprise. I'd never seen anything like it, and had no idea where to look to find the problem. Care to see if you can guess what it was? (Solution at the end.)
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Arrow's Max-1000: A gem for all the wrong reasons
I recently purchased a MAX-1000 development board from Arrow. It's a nice, small, FPGA development board for anyone interested low price. In the process, however, I discovered some amazing things about the FTDI FT2232H chip on board.
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Building a Simple Logic PLL
Phase-Locked Loops are components designed to lock an oscillator to the phase and frequency of an incoming oscillator. In this article, we'll present a very basic PLL algorithm that can, at high speed and within an FPGA, lock onto the phase of an incoming logic signal.
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Building a Numerically Controlled Oscillator
A Numerically Controlled Oscillator (NCO) plus a Digital to Analog (D/A) converter creates a Direct Digital Synthesizer (DDS)--something that can create a tone of any user-controlled frequency. Let's skip the D/A today, and discuss how to drive a sine wave generator to create that known frequency.
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Testing the fast, generic FIR filter
The last filter we presented was a high speed, generic, reconfigurable, FIR filter that can be used for many purposes. Since then, we've been working our way towards a framework for testing that filter. Today, let's build that test bench from the framework we've developed and see how well our filter actually works.
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Thank you!
O give thanks unto the LORD; for He is good!
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Measuring the frequency response of a filter under test
Our generic filtering harness development stopped short of measuring the frequency response of a test filter. Here, we pick back up the discussion and work through how you might measure the frequency response of a filter under test using Verilator.
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Building a prefetch module for the ZipCPU
The pre-fetch module is one of the fundamental components of any CPU. It is responsible for fetching instructions from memory. The ZipCPU prefetch is also an example of a Wishbone master, something worth looking at again in and of itself. This post adds a twist, though, to those two topics in that we'll also formally prove that this prefetch algorithm properly accesses the Wishbone bus.
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Generating more than one bit at a time with an LFSR
The typical LFSR development ends with logic that can create one bit per clock. What happens when you need many bits per clock, not just one? So let's continue our discussion of LFSRs and investigate how to calculate many LFSR bits per clock.
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An example LFSR
To many people, LFSRs magically produce random numbers. They are a confusing unknown. So let's look at an example 5-bit LFSR, and see what happens when we step through its logic.
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A Configurable Signal Delay Element
Many DSP applications have a need to delay a signal against itself by some period of time. Such delays are fundamental. They are also fairly easy to build.
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Building Formal Assumptions to Describe Wishbone Behaviour
The most critical component of any bus based system, such as a System on a Chip (SoC), is the bus interface. One failure of this interface can easily lock up the entire system. This post examines the Wishbone bus interface, and presents some formal properties that can be used to verify that a Wishbone master works.
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The Interface to a Generic Filtering Testbench
As we work our way through discussing digital filtering, and presenting multiple digital filters, we're going to need to test these filters. This article outlines, from the bottom up, a test harness that can be used to aid testing whether or not a digital filter produces the response one would desire.
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Good Software Engineering Principles Apply to Students Too
Just because you'll be turning in a one-time project for your class, doesn't mean you can ignore good software engineering principles. Those same principles might be the difference between getting your project working or not.
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Generating Pseudo-Random Numbers on an FPGA
At some point or other, when working with FPGAs, you will need a pseudorandom number sequence. Linear Feedback Shift Registers are commonly used for this purpose. Here, we discuss such registers and how to create them within Verilog.
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Some Simple Clock-Domain Crossing Solutions
Crossing clock domains is one of those FPGA design topics that is strictly a hardware topic. By the time a software engineer starts his work, any CDC issues have likely been resolved. Not so for the FPGA designer. Let's examine several methods for crossing clock domains.
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My first experience with Formal Methods
I've just started trying formal verification methods based upon yosys and yosys-smtbmc this week. As a result, I've now found several subtle bugs within my FIFOs, things that I would never have found otherwise. This post shares some of my initial thoughts and experiences, as well as providing a short primer to the method.
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Just some notes to new readers of the ZipCPU blog
If you've just started reading the ZipCPU blog, welcome! Let's take a look at some upcoming topics.
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Implementing the Moving Average (Boxcar) filter
A fully generic filter can be difficult to implement within an FPGA, since FPGAs can only support a limited number of multiplies. One way of simplifying the problem is to use a moving average filter. Let's examine how to build one of these filters.
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FPGAs vs ASICs
While I like to lump both FPGA and ASIC development into a catch-all phrase 'digital logic', there are some very real differences between the two. Let's examine some of those differences together.
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It's all about the interfaces
If you want raw algorithmic speed, look no farther than an FPGA. However, before you start drooling over how fast an FPGA can run a task, take a moment to think about what it will take to get your data in and out of the FPGA at the speed you want the FPGA to run.
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Using AutoFPGA to connect simple registers to a debugging bus
Let's take a look at what it takes to add a simple, single-register component to an AutpFPGA based design. We'll look at and examine some simple peripherals, and look at how the components configuration file tells AutoFPGA how to connect the component to the rest of the design.
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A Brief Introduction to AutoFPGA
Many of my readers are aware that I am working on a project I've called AutoFPGA. AutoFPGA makes it easy to reconfigure a bus and reassign addresses when adding new components to a design. This post presents a high level overview of how AutoFPGA may be used.
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A CORDIC testbench
Building a test bench for a CORDIC with an arbitrary number of bits, both input, output, and phase bits, is not a trivial task. However, without knowing how good a component should be, it's hard to know whether or not the component works to its specification.
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A Cheaper Fast FIR Filter
After I last posted on how to build a generic FIR filter, a friend showed me a cheaper implementation. This post presents and examines that cheaper implementation.
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Understanding the effects of Quantization
If you are building DSP algorithms within FPGAs or other digital logic, it's important to know how your logic will handle finite bit arithmetic. This post just goes over some of the basic effects of quantization: what it is, and some simple means of modeling it to determine how it will affect your algorithm.
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Clocks for Software Engineers
If you have a software background, and you want to pick up digital design, then one of the first things you need to learn about is the clock. To many software engineers, the concept of a clock is an annoyance. Without using a clock, they can turn HDL into a programming language. Yet the clock they are ignoring is often the most fundamental part of digital design.
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Demonstrating the improved PWM waveform
Having posted on an improved form of Pulse Width Modulation, I've been asked to provide a demonstration of this capability illustrating that this technique actually works. So today we'll discuss the technique again and present performance measures showing how well this method of signal generation outshines its traditional PWM counterpart. Sample code is provided, so you can test it for yourself.
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Building a high speed Finite Impulse Response (FIR) Digital Filter
Digital Filtering is one of the most fundamental DSP operations. Further, because of their speed, FPGAs can filter things that nothing else can. This post will develop a simple, extensable, generic high speed re-programmable digital filter.
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Even I get stuck in FPGA Hell
Yes, even I get stuck in FPGA Hell from time to time. Here's a quick discussion of three problems where I got stuck recently: HDMI input, getting the debugging bus up and running, and an arbitrary clock rate generator. In each case, I present not only how I was stuck, but also how I got unstuck.
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Glad I went to ORCONF
My thanks go out to the ORCONF team for making this years conference a success!
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Off to ORCONF-2017!
This week, I'm off to ORCONF-2017 in Hebden Bridge, England. I'll be giving a presentation on AutoFPGA, and a quick update on the ZipCPU development.
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Reinventing PWM
A PWM output can often be used as a poor man's low-frequency digital to analog converter. Such outputs are so easy to create, that they often make sample problems for beginners. Here, we'll not only show an example of the beginners solution, but we'll also create a simple no-cost improvement that can be applied for audio signals.
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Big Money Engineering Integrity
This article is a true story of what happens when engineering integrity is lost at the big money government level. The result wasn't pretty.
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CORDIC part two: rectangular to polar conversion
The CORDIC algorithm we discussed can be used in more than one fashion. We've now discussed how to use it to calculate sine and cosine functions. Today, let turn the algorithm around and use the same method to generate polar coordinates from rectangular inputs--essentially the reverss of the last operation.
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Using a CORDIC to calculate sines and cosines in an FPGA
Having presented several simple means of calculating a sinewaves within an FPGA, we turn to a more powerful method today: the Coordinate Rotation Digital Computer, or CORDIC. Although this method has a higher latency than the two table based lookup methods, it also has the capability for much greater precision than either table method can provide.
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Building a quarter sine-wave lookup table
Since we've already discussed how to build a simple sine wave lookup table, as well as several general strategies for controlling pipeline logic, let's take a look at creating a sine wave from a quarter wave table. We'll also use this as an opportunity to discuss how to create pipelined logic in general.
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Debugging your soft-core CPU within an FPGA
We've already looked at the requirements for debugging a CPU in general, as well as how to debug a CPU in simulation. Let's now take a look at how to modify your soft-core CPU so that you can debug it when it is on an FPGA.
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The ZipCPU's pipeline logic
Having discussed several strategies for pipelining in general, we turn our attention to the strategy used for handling pipelining within the ZipCPU. Hence, we present the pipelining logic used by the ZipCPU, as well as the variable names you can search on in case you want to see in detail how a CPU can handle its pipeline logic.
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Rules for new FPGA designers
This year many students will try to take up digital design. Some of these students will enjoy their experience, many will not. Here are some tips to help keep you out of trouble, so your experience will be one of the more enjoyable ones.
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Two of the Simplest Digital filters
The simplest digital FIR filter out there is a simple adjacent sample averager. Here we present not only that filter, but also discuss how any Digital filter may be tested and proven.
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Strategies for pipelining logic
Pipelining logic is one of the most basic digital logic concepts. Many processing algorithms can naturally be pipelined--reducing logic and speeding up algorithm completion. However, most pipelines require some form of handshake signals. This post, therefore, discusses those handshaking signals, presenting several options that can be used depending upon the circumstances.
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What would cause you to lie?
Engineering integrity should not need to be discussed on any engineering forum. The honesty of every engineer should be assumed. That this is not the case, and that this needs to be discussed is unfortunate. It is, however reality. So, let's ask, what would it take for you to compromise your integrity?
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A Simple ALU, drawn from the ZipCPU
When it comes to building a CPU, an ALU may be the simplest part. This discussion examines how simple an ALU can be made to be, by examining the ALU within the ZipCPU.
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Series: Debouncing in Digital Logic
This completes our series on button bouncing, and the logic necessary to both measure and to eliminate button bouncing.
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Using a debug-bus to Measure Bouncing
While many other FPGA web sites discuss contact bounce and how to get rid of it, let's take a different approach here. Let's combine our debouncer with our measurement code, connect it to our debugging bus, a get a trace from within the FPGA indicating what was taking place.
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Measuring Contact Bounce
Now that we know that buttons don't behave like we would like, what would it take to measure that behavior? Let's measure not only the number of times a button changes, but also how long it takes from the initial change to the final change.
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How to eliminate button bounces with digital logic
Unilke LEDs, pushbuttons have a series of problems associated with them that make them difficult to use as part of debugging a design. They can be useful, but only after your debouncing logic has first been proven
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Visualizing Contact Bounce
Buttons when pressed often report more than one contact, or even more than one release. This post presents the result of measuring several such bounces.
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ZipCPU Advertising
Disqus support has been removed, since their advertising was not consistent with my strong Christian scruples. The ZipCPU blog is not, nor has it ever been, supported by advertising.
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Writing your own VCD File
If you ever decide you want to create your own scope, but not your own viewer, than knowing how to write a Value-Change Dump (VCD) file may be required. Here, we'll go over the basics of how to write such a file, as well as discuss the meanings of the most common parts of one.
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Linear Interpolation
An Overview of the Linear Interpolation Series
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Getting the basic FIFO right
A FIFO is a very basic component of any digital logic system. Getting the components and the timing right, though, can be a careful chore. Here, let's examine how to build a basic FIFO.
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Windows FPGA designers may not need a Linux machine ... yet
Many of the programs I use for FPGA design and debugging, such as verilator or GTKWave, run just fine under Windows when using Cygwin. Here's how to set up some Linux FPGA tools under Windows.
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How to build a simulation based debugger for your own soft-core CPU
While Verilator makes for a great simulator, gtkwave isn't the most intuitive way to debug a CPU. Rather than staring at incomprehensible wires, give your simulator the feel of a proper debugger using these techniques
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How to Debug a DSP algorithm
DSP algorithms are not like other algorithms when it comes to debugging. printf() and gtkwave just don't work as well. Let's look into an alternative.
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Rounding Numbers without Adding a Bias
If every operation adds to the number of bits required to represent the result, how do you get rid of bits? It's not nearly as simple as it sounds, since most of the methods for getting rid of bits bias the result one way or another. Here we'll examine a couple rounding methods, and discuss their problems, and also describe a solution.
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Bit growth in FPGA arithmetic
Integer arithmetic from a small domain, creates larger and larger numbers. Here, we'll quantify that effect.
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A Basic Upsampling Linear Interpolator
This blog article is the second in a series on rate conversion within DSP's. Specifically, we'll look at how to upsample an incoming signal from whatever rate it was given to you at, on up to any rate at or less than your FPGA's clock rate.
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Verilator doesn't find everything (today)
After posting the debugging bus stories, I was embarrassed to implement it on my own FPGA and not get immediate and perfect success. Verilator just doesn't find everything (today).
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Design Needs when Debugging a SoftCore CPU
There's more to designing a CPU than picking the instructions that the CPU must support. This blog post discusses the debugging facilities you are likely to want while you work to bring your design to fruition.
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The simplest sine wave generator within an FPGA
If you find yourself needing a sine wave within an FPGA, here's the simplest method(s) I know of creating one.
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Getting Started with the Wishbone Scope
This post describes how to get started with the wishbone scope in your own design. As a fun end result, we'll draw the information necessary to create a VCD file and thus a GTKWave plot from logic within your design
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Finishing off the debugging bus: building a software interface
This post completes the sequence on what it takes to build a debugging bus, by building a software controller to encode commands for and decode responses from the FPGA. Once built and integrated into your design, the dbgbus controller should be able to help you communicate with components within your FPGA
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Why you want a debug port into your FPGA
Just a quick picture of what you can do with the dbgbus once finished
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Simulating an FPGA through the debugging interface
Given the debugging interface just created, this post goes into how to go about simulating it via Verilator
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My own FPGA debugging philosophy
Many individuals have read my previous posts and have wondered what my design philosophy actually is. This post attempts to outline the general approaches I used to debugging my own FPGA designs
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Building a very simple wishbone interconnect
Having now built all of the components of a UART to wishbone bridge, it's time to build a test design that would use it. This article, therefore, discusses how to build the interconnect that will connect a single wishbone master to multiple wishbone slaves
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Taking a New Look at Verilator
Verilator is not a simulator in the sense of any of the other commercial HDL simulators on the market, yet it has some very unique capabilities when it comes to simulating components that you won't find in other simulation tools
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Putting our Debugging Bus RTL Components Together
We've now built all the individual components of an RTL based debugging bus. This post discusses how to put them all together.
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Sending bus idle notifications down the line
One difficult part of dealing with multiple serial interfaces is knowing which one has what port on it. We'll solve this problem on our FPGA debugging interface by adding a simple idle indication into our debugging port. With this capability, if we watch long enough, we can tell if the port is the right port or not.
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Why Use a Network Interface to your FPGA
Several of you have asked why the debug interface needs to be networked. What does that mean? and, is it worth the pain of a capability I don't think I need? This article discusses what it takes to network a debugging interface, therefore, and outlines why it isn't as difficult to do as it might sound.
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Support me on Patreon
The ZipCPU blog now has Patreon support! If you'd like to see this blog continue ...
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The debugging bus: a goal for FPGA interaction
We're now halfway through describing how to build a debugging bus within an FPGA for command, control, and feedback from that FPGA. This post takes a quick review of why we wish to do this.
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Adding interrupt reporting to our debugging bus
Now that we have a mostly working bus, let's add interrupt reporting as a simple feature to it
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How to send our bus results back out the serial port
We're close to having a working demonstration debug port to our design, but not quite there yet. This lesson focuses on how to turn the output words from our hexadecimal bus back into characters that we can then read on the output.
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No PI for you
Neither the units of degrees nor Radians make sense within an FPGA. This article discusses a better unit for angles within an FPGA.
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How to create bus command words, from a 7-bit data stream
Continuing our series on how to make a debugging bus, this article discusses how you can create bus command words from a stream of printable bytes.
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Minimizing FPGA Resource Utilization
At some time, every project will come face to face with the fact that FPGA resources equal dollars. Keep your dollar commitment small. Use the techniques in this post to keep your resource usage to a minimum.
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A College Student's Response to the FPGA Design Process
When I wrote the blog article about the FPGA design process, and how it differed between students, experts, and reality, one particular student's experiences were fresh in my mind. Here, he writes about his experiences from his own perspective.
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Building a Simple Wishbone Master
A discussion of how to build a simple bus master, such as you might wish to use to debug a wishbone-based system
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Building A Simple In-Circuit Logic Analyzer
Building your own in-circuit logic analyzer is a whole lot easier than it sounds
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Nearest Neighbor Interpolation
A simple presentation of how to handle resampling via a nearest-neightbor interpolation scheme.
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An Overview of a Wishbone-UART Bridge
I'd like to describe how to control a wishbone bus from an external command and control port. It's not that simple. This article discusses instead how one such approach works, decomposing the parts and pieces of it. It then outlines what a simplified control port structure might look like.
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Campus Sidewalks and FPGA Design
Sometimes you need to build something to fill a gap, before you know what to build. Here's an example.
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Controlling Timing within an FPGA
Every FPGA design needs to carefully control the timing of events. Here, we'll explore several ways to control timing within your design.
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The Actual FPGA Design Process
There seems to be a disconnect between the FPGA design process used by experts, and the students who request help from the online forums. This post examines that disconnect, pointing out the detail that's often missed.
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Building a simple wishbone slave
Bus slave interaction is actually fairly easy. Let's walk through an example wishbone bus slave and look at how it works.
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Bus Select Lines
If you want 8-bit access to a 32-bit bus, you'll need to incorporate the bus select lines into your logic. See how it's done here.
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FFT debugging
If you find you need to debug an FFT and that you are struggling to do so, the answer is that you need to go back to the basics of engineering. Working from the basics, debugging either an FFT or any other block will become straight-forward.
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Debugging an FPGA through the serial port--first steps
If you have a serial port, how might you use it to get information from your FPGA? Can you use it to help debug the rest of your design?
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That first serial port: Debugging when you are blind
A serial port can be a very useful way to get information from an FPGA. How can you avoid FPGA Hell when you are trying to get that first serial port up and running?
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Building a simple bus
For this article, we'll discuss the logic necessary to implement a very simple bus slave.
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Moving to memory
Blinking LEDs is a fun exercise, but eventually you will need to learn to walk to grow up. Within FPGA's, that means you'll need to learn how to deal with memory.
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A Vision for Controlling FPGA Logic
My approach to controlling and debugging an FPGA seems to be unique among those I share it with. Here I describe that approach for you, as a vision for where we might go here.
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Which comes first: the CPU or the peripherals?
Not whether or not the chicken or the egg came first, but in digital design which comes first: the CPU or the peripherals?
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Knight Rider
Knight Rider's car: KIT's LEDs can be a fun twist on a beginners first FPGA design
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FPGA Hell
FPGA Hell is where your design doesn't work, and you don't know why not. Here, we'll discuss basic approaches to avoiding FPGA Hell.
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Blinky
Your first FPGA design -- blinking an LED
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Most common Digilent FPGA support requests
After watching Digilent forum support requests for a year, they start to repeat into these categories
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Cannot be done
Never underestimate someone's creativity to make things work outside of spec
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