If you are interested in learning Verilog, there are already many tutorials online. Asic-world’s tutorial is perhaps the most complete on-line Verilog tutorial I know of. Nandland has an exceptional beginner’s tutorial as well. FPGA 4 Fun’s web site doesn’t really start at the bare basics, although it discusses how to build several basic peripherals. None of these tutorials, however, couple together all the tools needed to do design in one place.
The digital design student should be introduced immediately not only to the HDL language, but also to the tools necessary to debug his code. This includes not only Verilog (or SystemVerilog), but also a simulator (we’ll use Verilator, augmented at times with ncurses), waveform discumentation (wavedrom or even tikztiming), waveform display (gtkwave), and (my favorite) Formal Verification using SymbiYosys.
This beginners Verilog tutorial attempts therefore to fill some of the missing piecees in this void. My goal is to take a beginner from knowing C and a little C++, all the way to a serial port example using both receiver, transmitter and FIFO.
I’m also hoping to keep this tutorial fairly hardware generic. Hardware specific topics will be placed as bonus chapters between the lesson chapters.
- Wires, and combinatorial logic
- Registers and blinky
- Finite state machines
- Building a Wishbone Slave
- Building hello world, using a serial port transmitter
- Transmitting 32-bit data over the serial port
- Buttons: 2FF synchronizers, and debouncing
- Using FPGA block RAM
- Building the serial port receiver
- Building a FIFO for our serial port
This concludes the basic beginners tutorial.
I’ve thought about writing another more advanced tutorial to follow these ten lessons, but I haven’t yet settled on what such a tutorial might focus on. Useful topics would include a debugging bus, how to build and verify a CPU, as well as how to build slave peripherals that can be controlled by a CPU over a number of bus structures. Such bus structures could include Wishbone (my favorite), AXI-lite AXI, AHB, APB, Avalon, Tilex or I don’t know yet. We’ll have to see what the Lord wills.
Feel free to contact me if you have suggestions for where I might take this material next, or if you have any feedback on the above lessons! I’d love to hear from you.
Formal Verification Courseware
I also teach a course, An Introduction to Formal Methods, on behalf of SymbioticEDA. The course is offered either on-line or in-person and on-site. Feel free to examine the slides for this course here.
I currently offer the course in one of two fashions: on-line or in-person on-site. The format and the costs are subtly different.
From time to time, I teach the course on line using the Zoom teleconferencing application. When taught on-line, the course is structured as four 4-hr days of lessons. I offer this course for $750/person, for up to two people at a time.
Matt Venn also teaches this course on line as well, and often for a slightly lower price. Feel free to schedule with either of us if you are interested.
I also teach the course on-site as a two-day hands on course for up to six individuals at once. In this case, the course costs $4k plus whatever my travel costs might be.
Either way you choose to take the course, it comes with an evaluation license of the Symbiotic EDA Suite–providing access to not only VHDL and System Verilog, but also to the full System Verilog Assertion language.