Verilog and Formal Quizes
Formal Verification quizzes have long been a favorite on my twitter feed, hash tag #FVQuiz, so I thought I might start adding them to the blog itself. You should be able to find all of the information you need to solve each of the quizzes from within either the articles on the blog or the tutorials.
There are no scores. There is no chest beating. These are solely here for you to have some fun, to offer you something to test your skill against, and perhaps even to foster some discussion. As always, if you are unsure of any answer, then I would encourage you to run the tools and discover the answer for yourself before clicking through to read what the answer was.
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Quiz #23: Can this assertion fail?
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Quiz #22: Handling cover failures
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Quiz #21: Verifying all configurations of a design
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Quiz #20: Using $stable in a multiclock environment
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Quiz #19: Using disable iff in a concurrent assertion
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Quiz #18: Failures in clocked immediate assertions
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Quiz #17: Induction failures
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Quiz #16: Immediate assertions in the presence of asynchronous resets
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Quiz #15: Pass-through memory
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Quiz #14: Two nearly identical frequencies
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Quiz #13: Temporal assertion equivalences
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Quiz #12: Catching extraneous acknowledgments
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Quiz #11: Induction and clock enables
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Quiz #10: Checking stall conditions
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Quiz #9: Immediate assertions midst blocking assignments
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Quiz #8: Will this pass a bounded model check?
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Quiz #7: Returning to $past() and our counter again
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Quiz #6: Synchronous logic in Asynchronous contexts
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Quiz #5: Immediate vs Concurrent Assertions
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Quiz #4: If this counter is never triggered, can we prove it'll never leave zero?
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Quiz #3: Will formal verification prove this counter keeps its bounds?
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Quiz #2: Will this counter pass formal verification?
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Quiz #1: Will the assertion below ever fail?