This site is dedicated to helping students and other FPGA designers avoid FPGA Hell. FPGA Hell is the term I use to describe having a design that doesn’t work, and for which you don’t know why it isn’t working.
If you are stuck in FPGA Hell, then you are getting either no feedback at all from your logic, or alternatively the feedback you are getting doesn’t make any sense.
FPGA Hell will cost you your project deadline. It will cost you the ‘A’ that you would’ve otherwise received on your project, and might even cost you the ‘B’ or ‘C’. It may cause you to give up digital design entirely.
For the expert, FPGA Hell will literally cost you money. You will burn hours in FPGA Hell without making progress. You may have to abandon the project and lose any investment you’ve made into it. You might lose contracts entirely.
This site is dedicated to helping you avoid FPGA Hell.