Happy New Year everyone!
It’s now 2018. Shall we take a quick look at the top 10 posts from 2017? In case you missed them, here’s a recap:
This page, showing how to handle debouncing buttons, received 1,178 hits in 2017.
This page may have been the first real introduction to FIR filtering on ZipCPU.com, offering more details than the initial, two-simple filters article presented. It described how to build a generic FIR filter within an FPGA.
Although the blog has since moved on to discuss many other filtering implementations, this basic article was a winner that received 1,284 page views in 2017.
Although the CORDIC algorithm really isn’t anything new, this was still a winning article as it helped to explain to many how a CORDIC operates. As a result, this article received 1,347 page views in 2017.
This simple and short essay describes the reality that many FPGA developers have found themselves within: the code builds, it synthesizes, it can be placed onto an FPGA, but once there it doesn’t work. It also offers some approaches for getting out of FPGA Hell as well. This well loved article received 1,375 page views in 2017.
Thanks to a conversation with a friend at ORCONF this year, I learned that ASIC development is very different from FPGA development. Sure, they both share Verilog or VHDL as a base language, and they both use digital logic, but they are also very different disciplines. This article focuses on and describes those differences. It received 1,427 page views in 2017.
I guess I wasn’t expecting this article to end up on the top-ten list this year when I wrote it. It only describes a very simple prefetch module for the ZipCPU, not the fastest or the best prefetch module. Perhaps it was because it showed how a prefetch module could interact with a CPU, or perhaps it was because it showed how a prefetch module could be formally verified. Either way, this article ends up at number 6, with 2,003 page views during 2017.
Indeed, since this topic was so well received, I am looking forward to posting about the ZipCPU’s prefetch and cache module, and how that module may also be formally proven, in 2018.
This post discusses several different approaches to simple clock domain crossings. It discusses what clock domain crossings is, and when you need a clock domain crossing solution in the first place. This article received 2,152 page views.
This post discusses my first experiences with using formal methods via the open source yosys program and the associated yosys-smtbmc program. I applied these methods to a FIFO. Much to my surprise, the formal methods found bugs in my “working” FIFO implementation that I had never found using a traditional test bench methodology.
This post received 5,936 page views in 2017.
At the beginning of the fall 2017 semester, I put together a list of “rules” and pieces of advice for new FPGA designers. While these rules were hotly debated on the Hacker News website, they will still help to keep new FPGA designers out of a lot of debugging troubles.
This post received 11,530 page views.
The one post that received more page views than any other was the Clocks for Software Engineers post. This post examines many of the common problems that software engineers have when trying to “program” in Verilog or VHDL. It discusses the impact of for loops, and why the clock is so important.
In general, I make it a point not to post any of my articles to any news aggregators. This is based upon the Bible verse:
Let another man praise thee, and not thine own mouth; a stranger, and not thine own lips. (Prov 27:2)
Doing this also allows me to evaluate how well a particular article was, or was not received. If someone feels that the article was well written enough to post to an aggregator, then that tells me something about my audience.
It may have been about four days after I posted this article when someone read it and posted it on Hacker News. I was sitting at my desk at the time watching Google Analytics while doing other work when suddenly the number of page views spiked from 0-3 at a time to upwards of 700 views at once. (It’s probably more accurately a block average over a minute or two, but it shows on the screen as though they were all at once.) I then looked to find the article on Hacker News: it was the top article for several hours that night. Since then, it has often remained the top article people have read on a week by week basis.
This article tops the zipcpu.com charts at 57,033 page views in 2017.
If you find you’ve missed any of these articles, feel free to go back and read what others have enjoyed so much this year.
From my standpoint, I find these top ten articles, together with any e-mails from my Patreon supporters, are a guide to what topics might interest FPGA developers in the future. For example, based upon this list I’ll probably discuss some other (better?) approaches to sine-wave generation in this new year, how to build (and verify) a prefetch with an integrated cache, an asynchronous FIFO implementation, how to simulate a display using Verilator, and much more–but only if the Lord is willing.
Say not thou, What is the cause that the former days were better than these? for thou dost not enquire wisely concerning this. (Eccl 7:10)