If you are new here, I’d like to take this personal opportunity to welcome you to the ZipCPU blog!

I discuss FPGA design methodology, completed designs, DSP, formal methods, and more. I’ve also been known to tweet about the same as well. If you aren’t following me on twitter, then let me invite you to do so–or you’ll miss the weekly formal verification quizzes. The blog also has an RSS feed, and you are welcome to subscribe to it, although I have been known to wait some time after posting before updating the RSS feed.

If you are a beginner, the blog is loosely built so that the simpler topics are the older ones that you’ll find at the bottom of the page. I would therefore recommend you start reading the blog from the oldest articles to the newest. If you do so, you’ll also notice my methods have changed somewhat as well–I didn’t use formal methods at first. Perhaps one day I’ll organize all of my posts into a textbook. Such a textbook would be built around the premise that design engineers spend the most of their time debugging, and so it would focus on not only learning designs, but formal methods, simulation, and troubleshooting as well. As such, it would have the three thrusts of learning shown below.

Fig 1. Tentative Digital Design Learning Outline

Until that time, these posts will remain organized by date only, somewhat disorganized by ability level, and topically disorganized. While I have tried to sort the site by topic here, I’ve also discovered in the process that the major categories overlap, so that page has only been somewhat successful.

I also teach a two-day on-site course in formal verification using a commercial version SymbiYosys with support for VHDL, Verilog, SystemVerilog, and the full SystemVerilog assertion language. That course is more organized than these blog articles are. If you are interested, SymbioticEDA handles the scheduling on my behalf.

While I enjoy and welcome discussion, there is no discussion capability on this blog, and some topics just don’t fit in tweets. (Sorry.) Depending upon the type of discussion you would like, feel free to either ask on freenode’s #yosys or ##FPGA channels (you will need to get a free account) where I am known as ZipCPU, or alternatively on Reddit where I try to monitor both the FPGA and the yosys channels as well. If you ask a yosys question that is too difficult for me on reddit, I’ve been known to bring it up to Clifford at our weekly meetings, and answer it then. For such questions, reddit replies can take a couple of days.

You should also know that I am a Christian, and I am not ashamed of it. My own life has been dedicated to the service of Christ, and that now includes this blog. You can expect occasional articles on ethics, morality, and Christianity, verses at the end of each post, and even tweets on such topics from time to time.

My Christian beliefs are centered around a literal interpretation of the Bible. This includes a belief in a 6-day creation that took place roughly six-thousand years ago, a belief that God will cause the end of this world rather than any man-induced climate change, a firm belief that a free people should be an armed people, and more.

These beliefs have also led me to very strong right-wing political views.

My point is simply this: if these things will offend you, and they have offended some, then consider this as your fair warning.

If you are still interested in the ZipCPU blog, and even more if you find it valuable, then please consider supporting it. The ZipCPU blog is supported entirely through donations made by folks such as you, as well as my own love of helping and encouraging others. If you have benefited from the blog, then let me invite you to contribute a small sum on a monthly basis. Should you do so, you’ll also have access to another discussion forum on Patreon, where I write occasional messages to my sponsors, ask them about what topics might interest them and so on. I also have some designs, such as a WB to AXI-lite bridge, an AXI-lite to WB bridge, together with an AXI-lite formal property file, which are available to sponsors only. Using this formal property file, it’s easy to show how and why Xilinx’s example AXI peripheral code is broken.

Either way, welcome, and I hope to have had the opportunity to encourage you in your own journey while you are here.