It’s time again for ORCONF! For those who are not familiar with ORCONF, I like to think of it as the premier conference discussing Free and Open Source Silicon (FOSSI). You can read more about the conference here, or even read the abstracts of the presentations here, although this latter link is likely to go stale before ORCONF-2019. ORCONF tends to be a small conference, and nothing like the giant IEEE conferences I’ve been to in the past. I see this as a good thing, because it means I will actually have a chance to meet and say hello to everyone there.
This year, among the many wonderful presentations that I lined up, I am especially looking forward to Wilson Snyder’s presentation on a multithreaded version of Verilator. That could really transform my simulations!
Here’s his abstract:
Verilator 4.0 - Open Simulation Goes Multithreaded
The primary author of Verilator, the open source high-speed Verilog simulator, announces fresh for this meeting Verilator 4.0 with multithreading, and how you can get your designs the fast(est), free simulation.
Presented by Wilson Snyder, one of the primary authors of Verilator.
I will also be presenting this year, as I have the last two. My title is: Lessons learned while formally verifying the ZipCPU.
The ZipCPU is a three-year old CPU and ISA designed for low logic FPGA’s. One of the challenges of any CPU design, to include the ZipCPU, is coming up with a sufficiently robust test suite to exercise all of the possible logic flows within the CPU. While formal methods can be used for this task, they are traditionally viewed as too computationally expensive to formally verify something as complex as a CPU.
Contrary to this view, the ZipCPU has now been formally verified using SymbiYosys. As a result, many bugs have been found and fixed-bugs not found previously using canned test cases. Not only that, it has also become easier to modify the core CPU as necessary to achieve lower logic utilization, knowing that the solver will find any bugs in the updated implementations.
If you haven’t chosen to join us at ORCONF, then rest assured the staff are really good at posting the various presentations later. I will also post a copy of my slides on GitHub and link to them here, as I did last year. This is a small consolation, though, for missing the richness of actually meeting and discussing digital design topics with the likes of those who will be attending, or the opportunity to ask questions of the speakers.
On the other hand, if you will be joining us, then please take a moment to introduce yourself! I’d love to have the opportunity to meet those who have encouraged me over the last couple of years.
Making request, if by any means now at length I might have a prosperous journey by the will of God to come unto you. (Rom 1:10)