Projects List

Most of my time these days is spent working on commercial projects. Some of these are listed at

As of May, 2023, I'm also in the middle of generating the IP for a 10Gb Ethernet switch. The project is far from complete, but when finished it should also include HDMI and SATA controllers in addition to the virtual packet FIFOs I've written about. (The SATA controller is currently a work in progress, as is the GTX transceiver controller for the 10Gb Ethernet portion.) This project may also be a nice place to showcase my universal I2C controller--which has already started its service driving an OLED display and reading from a temperature sensor. If this is a project you are interested in, you can track my progress on the Ethernet portion here, and on the project in general here. As of this writing, we're only working on bringing up the first (draft) circuit board, so there's a lot more to come. Feel free to write me if you have further inquiries regarding this board.

I've also built a number of Open Source projects that may be of value to you:
  • The ZipCPU

    A fully functional, fully pipelined, 32-bit CPU designed for resource constrained FPGA environments. Includes GCC, Binutils, and Newlib support. Although designed to be powerful enough to run Linux, a Linux port has not yet been written. Many of the projects that follow use this CPU.

    Why doesn't the ZipCPU support Linux? For two primary reasons. 1) It's still missing a functional MMU, and 2) it's worked so well on my current projects that Linux hasn't been my priority.

    If you are interested in reading more about the ZipCPU, consider reading "A Quick Introduction to the ZipCPU's Instruction Set", "Instructions for building the GCC-based toolchain", or "Introducing the ZipCPU v3.0".

  • ZipCPU systems: The following are fully built, full featured systems for which the ZipCPU has been placed inside:
    • S6SoC

      This was one of my very first ZipCPU projects. It was a successful demonstration of how the ZipCPU could be made to fit on on even the smallest of FPGA's. Since the last build, the ZipCPU has evolved significantly, and I haven't used the Spartan 6 to revisit the project. The RTL, therefore, represents the state of the CPU when this project was last built and known to work on hardware.

      This same is true for the other projects that follow. The RTL in the master branch is the RTL that was used in the last hardware test or demonstration, and may not have been updated since even though the ZipCPU and/or other components have gone through many updates.

    • ArrowZip

      The MAX-1000 was a very inexpensive FPGA board sold by both Arrow and Trenz. (I'm not sure you can buy it anymore ...) This project places a ZipCPU on this board. It's also a demonstration of my (formally verified) Wishbone SDRAM controller.

    • OpenArty

      Demonstrates both the ZipCPU and AutoFPGA on a Digilent Arty A7 board.

    • ZBasic

      This is a bare bones, minimal ZipCPU system. If you wish to build a ZipCPU system and don't know where to start, this may be just the place. See this post for a discussion on how to get started with ZBasic.

      This was also (at one time) the project where I tested out new ZipCPU and AutoFPGA" features. However, with the latest release of the ZipCPU, I may not need this test ground anymore.

    • My original ZipCPU project was built for the Basys3

      Sorry, this project doesn't have a cool name. It was my first FPGA project, and one from before I was working on open source projects. One unique feature of this one is that I drive the VGA port from the flash, and so this project can be used to display arbitrary presentation types of images (i.e. static images) on a VGA screen. The VGA simulator from this project has since been posted on github as well.

    • VideoZIP is another system I'm working on. This one, though, is built entirely via the AutoFPGA program. The goal was (originally) to both receive HDMI signals, and transmit HDMI signals. As an unfunded project, it's not complete. However, I have managed to get the HDMI receive function working (just not the save to memory part), and it seems to be working well. Curiously, this unfinished project has formed the basis for many of my commercial projects. This is just a really capable board.

      There is also a branch offering RGMII based GbE support which has yet to be merged into the project as a whole. GbE support does work, the Tri-mode options haven't been well tested yet.

    • ICOZip, unlike the previous systems is a ZipCPU based system designed for the iCE40 on the ICO board. It can be built using the entirely open source yosys based tool-chain. This is another design built using AutoFPGA. Further, like the S6SoC design listed above, this is also a minimum logic design.

  • Digital Signal Processing (DSP) cores
  • Peripherals which may be used by the ZipCPU

    Computer systems don't make much sense these days without peripherals, and the ZipCPU is no different. The following is a truncated list of peripherals that have been used with the ZipCPU.

    • UART controller

      Contains both basic, and fully featured, serial port controllers

      Two features make this controller particularly valuable. The first is the four basic UART testing designs in the bench/verilog directory. When starting with any new design, before I know how the board designer labeled the UART wires, I use these basic designs to test them. Once tested, I can usually move quickly to a much larger and more complex design with a debugging bus within it. The second valuable feature is the Verilator UART simulator, which forwards a simulated designs UART ports to a TCP/IP network channel.

    • Wishbone based scope

      This plus the UART to wishbone bus converter I have might easily be considered the basics of any project I work on. Using this wishbone scope, I have debugged many, many interfaces--some listed here. I would recommend it for anyone interested in incorporating an internal logic analyzer (scope) into one of their projects.

      There is an AXI-lite version of the scope in the repository as well.

    • QSPI Flash controller

      A "universal" QSPI based flash controller, having DSPI and SPI options in the same repository. I'm now using this controller on almost all of my projects.

      All of these controllers can execute software in place (XIP).

    • I2C Controller

      This I2C controller repository began with two I2C controllers, a slave and a master, each wishbone controlled. Those two demonstrated themselves via the ability to read and write EDID display information as part of an HDMI project.

      Since writing the two of those, I've since come back to the project and added a Universal I2C controller. This controller was originally designed to handle unattended telemetry collection in a SONAR system. It's since been expanded to periodically collect temperature in an unattended fashion, or to drive OLED displays. It's also capable enough that I may even use it to implement an EDDC/CI capability in a display channel in addition to its original EDID purpose.

    • PWM Audio Controller

      We discussed this controller on the blog, and even demonstrated it as well.

    • GPS schooled clock

      This project takes, as input, the PPS signal from a PMod GPS and locks an internal counter to the signal. Using this core, you can record the time events to a precision of less than a fraction of a microsecond.

      This project is currently part of my OpenArty project, but I've applied it to other projects of mine as well. Currently, using the crystal oscillator on the Arty and the PMod GPS from Digilent, it can timestamp events within the design to within about 500ns or so of absolute time.

    • RTC Clock

      This is a very simple, almost beginner, exercise to create a clock in hours, minutes and seconds. It also includes a minutes and seconds count-down timer, a stop watch, and alarm capability.

    • SDSPI SD-card controller

      In order to use the SD Card on the XuLA board, I needed a SPI based SD-Card controller. While I intend to upgrade this to SDIO in the future, the SPI based controller is still valuable for some designs.

      Since the original usage, I've been able to demonstrate reading and writing files files from/to the SD Card. Even better, I can boot the ZipCPU off of a program stored on the SD card. Lord willing, this could make a nice post.

    • FM transmitter hack

      Just to prove FPGA's are in no ways inferior to Raspberry PI's, this peripheral can be used to turn your GPIO pins into an ad-hoc FM transmitter.

    • WBPMIC

      A very simple controller designed to read from Digilent's MEMs microphone PMod.

    • WB Oled, a controller for the Digilent PMod OLEDrgb display

      A special feature of this design is the GTKmm based simulation component, allowing you to visually "see" what the controller would be placing on the screen.

    • ICAPE Interface

      Xilinx's internal configuration access port provides some very useful features. Getting it running initially, though, was a touch of a challenge. This project captures what it takes in a Wishbone peripheral format.

    • VGA Simulator

      While not technically a "peripheral that may be used by the ZipCPU", the VGA simulator is a very important part of any graphical development. A not-yet-released version simulates HDMI as well. Using the simulator, you will be able to run your code within Verilator and visualize the output within a GTK window on your computer screen--with no hardware required beyond your desktop machine.

I've also been known to offer a two day Introduction to Formal Methods course to teach Verilog and VHDL developers how to use SymbiYosys in a "formal first" strategy.

    Traditionally, the price of formal methods has limited their use to small teams of verification engineers within large corporations. Today, SymbiYosys lowers the price of formal verification tools to the point where every RTL developer can use them.

    The course teaches formal verification from the basics through bounded model checking and induction steps. Specific topics discussed include dissimilar clocking, abstraction, invariants, arbitrary values, and more. Examples will be drawn from counters, SPI interactions, SDRAM controllers, cache implementations, peripheral bus interaction, and more.

    This course can be booked for corporate training on-site. Please contact me for details.

Most, but not all, of my projects have been released under the GPLv3 license. They may be built with Verilator without violating this license. Indeed, the license allows you to build your own projects using these components. Sadly, going beyond that limit gets into a legally gray area at this time. Hence, if you find this license insufficient for your needs, please contact me and I'll be glad to sell you a proprietary license customized to meet your needs. A key exception to this rule is my Wishbone and AXI bus interconnects, bridges, and other components project, which has been released under Apache 2 to encourage its widespread acceptance and adoption.