Blog Topics

The below list of topics includes both those things that I’ve already blogged about and some of those things I’d still like to blog about. Those with links are things I’ve blogged about.

If you are starting out with an FPGA design from scratch, then I’d like to recommend some quick resources for you. First, you’ll want to read my Rules for new FPGA designers. After that, let me invite you to try out my beginner’s tutorial. The intermediate tutorial is a work in progress as I write this. You might wish to check it to see how far I’ve gotten with it. Perhaps what’s there will be valuable for you anyway.

How to Debug an FPGA

If you are coming to the FPGA world from the big software world, you will find that FPGAs can be very difficult to debug. In this series, we’ll work through how to debug FPGAs, from blinky to a networked debugging controller.

• We already started with blinky, and how blinky can be used to debug an FPGA

• What is simulation? This is something you need to learn very early on to be successful.

• A Vision for controlling (and debugging) an FPGA, to outline where we wish to go

• Getting that first UART working – I returned to discuss my serial port later, in Using Sequence Properties to Verify a Serial Port Transmitter

• Debugging by simple bus address, i.e. requesting and then reading values from a bus telling you what things are doing now. This includes discussing CE

• An example discussing how to debug an FFT. This also presents a method for “single-stepping” an FPGA that I find very powerful when debugging.

  • I later came back to the topic of an FFT, presenting how I formally verified the FFT itself. I then came back again to discuss how you might debug an AXI Streams such as the FFT’s input in general.

• Building a debug control interface

  • An overview of an example UART-wishbone bridge built for debugging purposes

  • How to build command words for our debuging wishbone interface

  • A simple wishbone bus master

  • How to turn responses from the wishbone bus into an output serial stream

  • Adding interrupt support to the debug port

  • Adding a debug port idle indicator, so that we can tell this is a valid debug port

  • Connecting stream components together

  • A simple wishbone interconnect

  • How to set up a test bench to prove this works

  • An outline of how the software controller will work

  • How to build a software controller for the debug interface

  • How to get started with a wishbone scope, using our example design to read internals of our logic and to write out a VCD file that we can later examine.

• How to place a logic analyzer within your design, and to get the most use out of it

  o An description of how to build a bus-based scope

  o How to write your own VCD file so that you can see the results of your own scope within GTKwave

• Contact Bounces: A short series starting with a presentation of contact bouncing, and ending with an example design that can measure (and mitigate) bounces.

• Getting rid of the umbilical: moving your debugging channel to TCP/IP

Open Source FPGA Tools

• Looking at Verilator

  • Verilator doesn’t find everything (today)

  • Using Verilator in a multi-clock environment

• yosys-smtbmc, and the formal methods it allows

  • Are formal methods really all that hard?

  • An Exercise in Formal Induction

  • What does formal development look like in practice?

  • How to Formally Describe and Verify an Asynchronous Design: a clock switch

  • Will Formal methods ever find a bug in a “working” CPU: the ZipCPU?

  • Using Invariants in Formal Verification.

    This article is now deprecated. The method described within is known to passing broken designs. See Swapping assumptions and assertions doesn’t work for more info on that.

  • Formally verifying components with memory. While the example in this article cover’s the formal verification of a block RAM, the properties discussed apply to any memory-type controller

  • My design works in simulation, but not in hardware. Can formal methods help me?

  • The problem with a test bench approach to formal methods

• Makefiles for formal proofs with SymbiYosys

  Since writing this article, the format I was using to control parameters within my design from the SymbiYosys script. The best way to do that now is with Python code insertion into the SymbiYosys file. You can find an example of that with the ZipCPU’s SymbiYosys script.

• Using an open source VGA simulator

• Just how long does a formal proof take to finish?

• Is formal verification enough, or is simulation required?

Basic FPGA Design

• The real FPGA design process, and the student’s response

• It cannot be done

• Knight Rider LEDs

• Generating Timing

• Minimizing LUTs

• Strategies for Pipelining logic within an FPGA

• How to handle pipeline scheduling

• How to design a state machine

  This is handled in the tutorial, lesson 3.

• Project Ideas: the PMod AMP2

• Handling clock domain crossings

  • Formally verifying the synchronizer for an asynchronous reset

  • Using a FIFO to pass data from one clock domain to another

• Reasons why Synthesis might not match Simulation

• Rules for new FPGA designers

• Breaking all the rules to create an arbitrary clock signal

• Lessons in Hardware Reuse

How to Build and Debug a Softcore CPU

• Building and formally verifying a general purpose ultra-micro controller

• How to debug a CPU core for an FPGA

  • Which came first: the CPU or the peripherals?

  • Thinking about the debug capabilities you will need, before you build

  • Debugging your CPU using Verilator

  • The structure of a simple ALU

  • The first ZipCPU prefetch

  • How the ZipCPU handles its pipeline logic

  • Mystery post: The ugliest bug I’ve ever encountered

  • Updating ZipCPU files

  • Building the ZipCPU toolchain, and demonstrating its pipeline

    Besides building the toolchain, this post offers a fun way to view how the logic moves its way through the ZipCPU as a result of the three separate ZipCPU prefetch modules.

  • Building and using an example ZipCPU demonstration design: ZBasic

    This discussion also includes a demonstration of what it takes to run 4x4x4 Tic-Tac-Toe on the ZBasic architecture.

  • Debugging your CPU while on the FPGA

    Here, we discuss how the ZipCPU can be halted, stepped, and even reset from the debugging bus.

  • Building a compromise prefetch module – one that isn’t as light on logic as the basic prefetch, but yet offers more performance than the prefetch and cache module.

  • Building Formally Verifying an Instruction Cache

  • The ZipCPU’s interrupt controller

  • Profiling your CPU using Verilator

    This will be about how I was able to measure, and optimize, every clock used by my CPU (as implemented on the XuLA2-LX25 when running the Dhrystone benchmark.

  • Debugging your CPU using a wishbone scope, when you have no debugging bus to work with

  • Building a better Verilog Multiply for the ZipCPU

• How to debug the ZipCPU when running the ZipOS found on the S6SoC

  o How a really simple Operating System works.

• Why does blinky make a CPU appear to be so slow?

• The ZipCPU meet blinky discussing how to run blinky across multiple threads

Wishbone Bus

• Moving to Memory, outlining why a bus is necessary

• Building a very simple bus, as a basis for building more complex bus structures

• How to build a Simple Wishbone Bus Slave

  – An example of a simple timer peripheral

  – An example of a flash memory controller, and it’s big brother, the QSPI flash controller

• The Wishbone Bus Select Lines

• A simple wishbone bus master

• A pipeline (input) aware wishbone bus master

• Formally proving that a wishbone master conforms to the standard

• Building a DMA bus master

Avalon Bus

• Formal properties of an Avalon bus component

AXI Bus

• Using a formal property file to verify an AXI-lite peripheral

• Buildng a custom yet functional AXI-lite slave

• The most common AXI mistake

• Understanding AXI addressing

• Examining Xilinx’s AXI demonstration core

• Building a Skid Buffer for AXI Processing

• Building the perfect AXI4 slave

• Xilinx deleted this post

• Connecting lots of slaves to a bus without using a lot of logic

• AXI Verification, the story so far

• 2019: AXI Meets Formal Verification

• Building an AXI-Lite slave the easy way

• Locally resetting an AXI component

• Building a basic AXI Master

• Debugging AXI Streams

• The hard part of building a bursting AXI master

• Run length encoding with an AXI stream

• Formally verifying register handling

• Common AXI Theme’s on Xilinx’s Forum

• Building a Simple AXI-lite Memory Controller for the ZipCPU

• Examining Xilinx’s AXI-lite Slave Design in VHDL

• Examples of AXI4 bus masters

• Measuring AXI latency and throughput performance

• AXI Handshaking Rules

• Upgrading the ZipCPU’s memory unit from AXI4-lite to AXI4

• Creating a simple AXI-Lite Master for the Hexbus

Interconnects

• AutoFPGA – a component aggregator

• Connecting a single-clock access component

• AutoFPGA’s linker script support gets an update

• Logic usage and decoding return results with cascaded multiplexers

• Lessons learned while building crossbar interconnects

• Technology Debt and AutoFPGA, the bill just came due

• Understanding AutoFPGA’s address assignment algorithm

• Building a Protocol Firewall

SoC + FPGA Architecture

• How to interact with an FPGA from a CPU

• Connecting a more generic component (ex flash, or SDRAM)

CPU design topics

• An overview of the ZipCPU instruction set

• How to build a back-end for GCC and/or binutils

• Debugging a CPU

• Putting the pieces together to build a data recorder

• How to build a back-end for your soft-core using GDB

DSP Topics

• Quantization error analysis

• Representing angles within an FPGA

• Debugging DSP algorithms

  o A basic histogram implementation, and then what happened when I went to use it

• Interpolation

  o Nearest Neighbour

  o Series: How to build a Linear Interpolator

  o Interpolation is just convolution

  o Quadratic interpolator

  o A filter based upsampling interpolation method

  o Polynomial Interpolation a.la Harris

  o Why splines are entirely inappropriate for real-time DSP

• CIC Filters

  o CIC upsampler

  o CIC downsampler

• Sine, Cosine, and Arctangent calculation

  o Table based sin/cos generation

  o Quarter wave table based sin/cos generation

  o What is a CORDIC, and how do I use it?

  • Generating Sin/Cos using a CORDIC

  • Using a CORDIC as a phase measuring device

  • The basic CORDIC test-bench

  • Basic logic design of a numerically controlled oscillator

  • Downconverting an incoming signal using a CORDIC

  • Generating AM, FM, and QAM types of signals using the CORDIC

  o A quadratic table based sin/cos generator, optimized for reduced phase noise and reduced spur energy. This requires two multiplies, and so it improves performance over the CORDIC approach

• Some general topics on Filtering

  o High speed filtering. These filters will run at your system clock speed, or not at all.

  • A pair of very simple digital filters

  • The Moving average filter

  • High speed FIR implementation

    • An improved high-speed implementation

  • High speed symmetric FIR implementation

  • Halfband FIR implementation

  • Hilbert Transform

  o Low-speed filtering. These filters run N times slower than your system clock speed. They are more efficient, if you can use them.

  • In general, these will be the same filters as their high speed counterparts.

  • A Generic (slow) FIR filter.

  • A cascaded slow FIR filter. This article will present an approach that allows you to cascade filter blocks together in order to implement a longer filter.

  • A symmetric slow FIR filter. This article modifies the generic (slow) FIR filter, in order to optimize it to exploit the linear phase relationship within it. This article goes through the background of why a symmetric filter is, as well as why such an implementation is superior to the generic one.

  o Building a delay

  o Estimating a filter’s cost

• Multi-rate signal processing

  o Implementing a downsampler and filter

• How to test a digital filter

  o Improved PWM: How to generating a cheap audio signal from an I/O pin

  o Testing the improved PWM signal

  o Building a generic filtering test harness

  • Evaluating the filter’s frequency response

  • Testing a generic filter using the test harness

  o Finding IIR limit cycles

• Generating a pseudorandom noise sequence

  o An Exampe LFSR

  o Getting many bits per clock from an LFSR

• Digital PLL design

  o A logic PLL, running at the system clock rate

  o Adjusting our logic PLL to handle I+Q

  o PLLs with better (CORDIC-based) phase estimators

  o Using a PLL together with a FIFO, for asynchronous sample rate conversion

• FFT and other spectral estimation topics

  o Cheap spectral estimation

  o An Open Source Pipelined FFT

  o Implementing a pre-FFT window function

  o Building a scrolling raster framebuffer

  o Color mapping the FFT’s results to the framebuffer

  o Maximally resolved FFT window functions

  o Optimizing the window function for high spectral resolution

• Discrete Fourier Transform Filter Banks. (Teaser)

Hardware reviews

The ZipCPU blog isn’t really about hardware reviews. That said, there have been several posts I’ve written that have highlighted one piece of hardware or another, so it’s worth listing them specially here.

• Digilent’s Digital Discovery

• Arrow’s Max-1000: A gem for all the wrong reasons

• Why I like formal: The ZipCPU and the ICO board

• The TinyFPGA

• Debugging a Cyclone-V

• Introducing the ArrowZip ZipCPU design, featuring the Max-1000