Intermediate Verilog Tutorial

This intermediate tutorial continues where the basic Verilog tutorial left off. It continues with the original tutorial’s goals of:

1. Generic hardware

   I’m going to do my best here, although many of the designs and projects will require some extra hardware. Examples might include a VGA (or HDMI) output port. These projects may still be simulated if you don’t have the hardware, or perhaps just reviewed and skipped.

2. Formally verified designs

   We’ll continue the tradition from the first tutorial of formally verifying everything.

3. Verilator based entire-design simulation

   As with the first course, there will be some amount of C++ programming associated with building and using hardware emulators in this course. Don’t let this surprise you.

4. One (or more) student level projects per lesson

The goal of this tutorial is to add a system bus to the mix, and to thus build components of that bus. We’ll start out building slave components, but then move onto building bus masters as well. In order to keep bus generation and connectivity generic across FPGA architectures, we’ll use AutoFPGA to build an interconnect that can hold everything together.

There is a strong likelihood that not everyone working through this course will have all of the required hardware for every lesson.

As before, I’ll provide the files necessary for each lesson, to save the student the pain of typing everything in. In order to make certain there’s learning involved in the exercises, I expect to provide broken examples that need to be fixed. Finding and fixing these errors should (hopefully) be one of the least onerous ways of learning the lesson(s). Of course, students are still welcome to type the lesson exercises in from beginning to end on their own.

Learning to use the Bus

The general outline of the course is shown in Fig. 1 below and discussed in this blog article.

Fig 1. Course structure

The course material will be written for the Wishbone bus. Students are invited to use other bus types if they wish–to include for example AXI-Lite or even AXI. AutoFPGA currently supports all three bus standards, and can be used to build interconnects as necessary for any of those standards.
AutoFPGA’s support is built upon the bus structures found in the wb2axip set of bus bridges and other odds and ends. In particular, AutoFPGA will connect a design to one (or more) of the crossbars found within that repository.

Bus Slaves

Enough background, let’s get into the course material itself.

0. Course overview and design principles
1. WIP: Your first bus slave: GPIO/LEDs
2. Bus Bridging: Wishbone to AXI-Lite
   • Bridge to AXI-Lite[TGZ], [ZIP]
3. WIP: Generating a bus-controlled Audio Tone
   • Tone generator [TGZ], [ZIP]
4. WIP: Using on-board memory
   • A wavetable LED controller [TGZ], [ZIP]
5. WIP: Bus Scope [TGZ] [ZIP]
6. (Not yet written:) Flash Memory

Video

7. (Not yet written:) VGA
8. (Not yet written:) Sprites
9. (Not yet written:) Asynchronous FIFOs
10. (Not yet written:) Frame Buffer

Bus Masters

11. (Not yet written:) SPI based A/D Controller
12. (Not yet written:) Data Recorder
13. (Not yet written:) Music Box

CPUs

14. (Not yet written:) A Simple Microcontroller
15. (Not yet written:) Bare bones debugger
16. (Not yet written:) Program Loader
17. (Not yet written:) Linker Scripts
18. (Not yet written:) Bootloader
19. (Not yet written:) Pipeline based CPU
20. (Not yet written:) Cache
21. (Not yet written:) FAT Filesystem

Watch this page! If the Lord wills, there will be more to come!

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