Digital Signal Processing Posts

Spectrograms need Window Functions
Let's examine the basics of localizing signal energy in time and frequency bins, showing from first principles the need for a window function how overlap choice affects this choice of taper. We'll then look at how to implement a window function in both C++ and Verilog.

Building a Downsampling Filter
A digital downsampler is a combination of both a digital filter and an every Nth element selector. It's basic. Formally verifying it, perhaps not quite so basic.

Debugging AXI Streams
Debugging a broken AXI stream is a common problem appearing over and over again on various forums. InCircuit Logic Analyzers don't do the problem justice, and often instead hide critical details of the stream protocol. In this article, we'll look at how to build a key piece of scaffolding you might use to debug an AXI stream processor.

Cheap Spectral Estimation
Placing an FFT inside an FPGA just to debug what may be going right or wrong with your DSP algorithm can be a costly addition. Let's look instead at an AutoCorrelation based alternative which can get us to roughly the same result, while moving the difficult math out of the realtime flow and into a nearby processor.

Adjusting our logic PLL to handle I&Q
By making some simple changes to the phase estimator of our logic PLL, it can be made to run in a quadrature I+Q context

A Histogram Gone Bad
I took my working histogram component, and placed it into a full design. It didn't work. Let's take a look at what happened.

Using a Histogram to Debug A/D Data Streams
Histograms are an important part of debugging a data channel. Let's take a look at some pictures, and then discuss how to go about implementing one

An Open Source Pipelined FFT Generator
Not having an open source FFT implementation can make simulating DSP algorithms with an open source simulator such as Verilator nearly impossible. Now there's a highly configurable open source alternative. Better yet, this alternative has been formally verified. We'll discuss that FFT, and how the formal verification was accomplished, here.

A Slow but Symmetric FIR Filter Implementation
The cost of an FIR filter is usually measured by the number of multiplies required to calculate an output. If you want to implement a better filter, you only need to be able to afford more multiplies. However, if the filter is symmetric, and most FIR filters are, then a little cleverness will allow you to implement the same filter with half as many multiplies.

Quadratic fits are entirely inappropriate for DSP
If you ever need to estimate a signal's value between samples points, don't use a quadratic fit. There are much better techniques out there which don't suffer from the discontinuities and high frequency distortions associated with a simple quadratic fit. Want to see an example?

Interpolation is just a special type of convolution
One of the more profound DSP lessons I ever learned was that most practical interpolators can be understood as convolutions. This is important because it means that interpolation function have frequency responses, and that their performance can be understood by examining this response.

A better filter implementation for slower signals
All of the filter implementations we've presented so far are high speed implementationsappropriate for signals at or close to the system clock rate. These implementations, however, end up being very resource expensive when all you want to do is to filter a much slower signalsuch as an audio signal. This post, therefore, presents an alternative that is more resource efficient for audio signals.

Building a Simple Logic PLL
PhaseLocked Loops are components designed to lock an oscillator to the phase and frequency of an incoming oscillator. In this article, we'll present a very basic PLL algorithm that can, at high speed and within an FPGA, lock onto the phase of an incoming logic signal.

Building a Numerically Controlled Oscillator
A Numerically Controlled Oscillator (NCO) plus a Digital to Analog (D/A) converter creates a Direct Digital Synthesizer (DDS)something that can create a tone of any usercontrolled frequency. Let's skip the D/A today, and discuss how to drive a sine wave generator to create that known frequency.

Testing the fast, generic FIR filter
The last filter we presented was a high speed, generic, reconfigurable, FIR filter that can be used for many purposes. Since then, we've been working our way towards a framework for testing that filter. Today, let's build that test bench from the framework we've developed and see how well our filter actually works.

Measuring the frequency response of a filter under test
Our generic filtering harness development stopped short of measuring the frequency response of a test filter. Here, we pick back up the discussion and work through how you might measure the frequency response of a filter under test using Verilator.

Generating more than one bit at a time with an LFSR
The typical LFSR development ends with logic that can create one bit per clock. What happens when you need many bits per clock, not just one? So let's continue our discussion of LFSRs and investigate how to calculate many LFSR bits per clock.

An example LFSR
To many people, LFSRs magically produce random numbers. They are a confusing unknown. So let's look at an example 5bit LFSR, and see what happens when we step through its logic.

A Configurable Signal Delay Element
Many DSP applications have a need to delay a signal against itself by some period of time. Such delays are fundamental. They are also fairly easy to build.

The Interface to a Generic Filtering Testbench
As we work our way through discussing digital filtering, and presenting multiple digital filters, we're going to need to test these filters. This article outlines, from the bottom up, a test harness that can be used to aid testing whether or not a digital filter produces the response one would desire.

Generating PseudoRandom Numbers on an FPGA
At some point or other, when working with FPGAs, you will need a pseudorandom number sequence. Linear Feedback Shift Registers are commonly used for this purpose. Here, we discuss such registers and how to create them within Verilog.

Implementing the Moving Average (Boxcar) filter
A fully generic filter can be difficult to implement within an FPGA, since FPGAs can only support a limited number of multiplies. One way of simplifying the problem is to use a moving average filter. Let's examine how to build one of these filters.

A CORDIC testbench
Building a test bench for a CORDIC with an arbitrary number of bits, both input, output, and phase bits, is not a trivial task. However, without knowing how good a component should be, it's hard to know whether or not the component works to its specification.

A Cheaper Fast FIR Filter
After I last posted on how to build a generic FIR filter, a friend showed me a cheaper implementation. This post presents and examines that cheaper implementation.

Understanding the effects of Quantization
If you are building DSP algorithms within FPGAs or other digital logic, it's important to know how your logic will handle finite bit arithmetic. This post just goes over some of the basic effects of quantization: what it is, and some simple means of modeling it to determine how it will affect your algorithm.

Demonstrating the improved PWM waveform
Having posted on an improved form of Pulse Width Modulation, I've been asked to provide a demonstration of this capability illustrating that this technique actually works. So today we'll discuss the technique again and present performance measures showing how well this method of signal generation outshines its traditional PWM counterpart. Sample code is provided, so you can test it for yourself.

Building a high speed Finite Impulse Response (FIR) Digital Filter
Digital Filtering is one of the most fundamental DSP operations. Further, because of their speed, FPGAs can filter things that nothing else can. This post will develop a simple, extensable, generic high speed reprogrammable digital filter.

Reinventing PWM
A PWM output can often be used as a poor man's lowfrequency digital to analog converter. Such outputs are so easy to create, that they often make sample problems for beginners. Here, we'll not only show an example of the beginners solution, but we'll also create a simple nocost improvement that can be applied for audio signals.

CORDIC part two: rectangular to polar conversion
The CORDIC algorithm we discussed can be used in more than one fashion. We've now discussed how to use it to calculate sine and cosine functions. Today, let turn the algorithm around and use the same method to generate polar coordinates from rectangular inputsessentially the reverss of the last operation.

Using a CORDIC to calculate sines and cosines in an FPGA
Having presented several simple means of calculating a sinewaves within an FPGA, we turn to a more powerful method today: the Coordinate Rotation Digital Computer, or CORDIC. Although this method has a higher latency than the two table based lookup methods, it also has the capability for much greater precision than either table method can provide.

Building a quarter sinewave lookup table
Since we've already discussed how to build a simple sine wave lookup table, as well as several general strategies for controlling pipeline logic, let's take a look at creating a sine wave from a quarter wave table. We'll also use this as an opportunity to discuss how to create pipelined logic in general.

Two of the Simplest Digital filters
The simplest digital FIR filter out there is a simple adjacent sample averager. Here we present not only that filter, but also discuss how any Digital filter may be tested and proven.

Linear Interpolation
An Overview of the Linear Interpolation Series

How to Debug a DSP algorithm
DSP algorithms are not like other algorithms when it comes to debugging. printf() and gtkwave just don't work as well. Let's look into an alternative.

Rounding Numbers without Adding a Bias
If every operation adds to the number of bits required to represent the result, how do you get rid of bits? It's not nearly as simple as it sounds, since most of the methods for getting rid of bits bias the result one way or another. Here we'll examine a couple rounding methods, and discuss their problems, and also describe a solution.

Bit growth in FPGA arithmetic
Integer arithmetic from a small domain, creates larger and larger numbers. Here, we'll quantify that effect.

A Basic Upsampling Linear Interpolator
This blog article is the second in a series on rate conversion within DSP's. Specifically, we'll look at how to upsample an incoming signal from whatever rate it was given to you at, on up to any rate at or less than your FPGA's clock rate.

The simplest sine wave generator within an FPGA
If you find yourself needing a sine wave within an FPGA, here's the simplest method(s) I know of creating one.

No PI for you
Neither the units of degrees nor Radians make sense within an FPGA. This article discusses a better unit for angles within an FPGA.

Nearest Neighbor Interpolation
A simple presentation of how to handle resampling via a nearestneightbor interpolation scheme.