Blog Posts

  • Some Simple Clock-Domain Crossing Solutions

    Crossing clock domains is one of those FPGA design topics that is strictly a hardware topic. By the time a software engineer starts his work, any CDC issues have likely been resolved. Not so for the FPGA designer. Let's examine several methods for crossing clock domains.

  • My first experience with Formal Methods

    I've just started trying formal verification methods based upon yosys and yosys-smtbmc this week. As a result, I've now found several subtle bugs within my FIFO's, things that I would never have found otherwise. This post shares some of my initial thoughts and experiences, as well as providing a short primer to the method.

  • Just some notes to new readers of the ZipCPU blog

    If you've just started reading the ZipCPU blog, welcome! Let's take a look at some upcoming topics.

  • Implementing the Moving Average (Boxcar) filter

    A fully generic filter can be difficult to implement within an FPGA, since FPGA's can only support a limited number of multiplies. One way of simplifying the problem is to use a moving average filter. Let's examine how to build one of these filters.

  • FPGAs vs ASICs

    While I like to lump both FPGA and ASIC development into a catch-all phrase 'digital logic', there are some very real differences between the two. Let's examine some of those differences together.

  • It's all about the interfaces

    If you want raw algorithmic speed, look no farther than an FPGA. However, before you start drooling over how fast an FPGA can run a task, take a moment to think about what it will take to get your data in and out of the FPGA at the speed you want the FPGA to run.

  • Using AutoFPGA to connect simple registers to a debugging bus

    Let's take a look at what it takes to add a simple, single-register component to an AutpFPGA based design. We'll look at and examine some simple peripherals, and look at how the components configuration file tells AutoFPGA how to connect the component to the rest of the design.

  • A Brief Introduction to AutoFPGA

    Many of my readers are aware that I am working on a project I've called AutoFPGA. AutoFPGA makes it easy to reconfigure a bus and reassign addresses when adding new components to a design. This post presents a high level overview of how AutoFPGA may be used.

  • A CORDIC testbench

    Building a test bench for a CORDIC with an arbitrary number of bits, both input, output, and phase bits, is not a trivial task. However, without knowing how good a component should be, it's hard to know whether or not the component works to its specification.

  • A Cheaper Fast FIR Filter

    After I last posted on how to build a generic FIR filter, a friend showed me a cheaper implementation. This post presents and examines that cheaper implementation.

  • Understanding the effects of Quantization

    If you are building DSP algorithms within FPGA's or other digital logic, it's important to know how your logic will handle finite bit arithmetic. This post just goes over some of the basic effects of quantization: what it is, and some simple means of modeling it to determine how it will affect your algorithm.

  • Clocks for Software Engineers

    If you have a software background, and you want to pick up digital design, then one of the first things you need to learn about is the clock. To many software engineers, the concept of a clock is an annoyance. Without using a clock, they can turn HDL into a programming language. Yet the clock they are ignoring is often the most fundamental part of digital design.

  • Demonstrating the improved PWM waveform

    Having posted on an improved form of Pulse Width Modulation, I've been asked to provide a demonstration of this capability illustrating that this technique actually works. So today we'll discuss the technique again and present performance measures showing how well this method of signal generation outshines its traditional PWM counterpart. Sample code is provided, so you can test it for yourself.

  • Building a high speed Finite Impulse Response (FIR) Digital Filter

    Digital Filtering is one of the most fundamental DSP operations. Further, because of their speed, FPGA's can filter things that nothing else can. This post will develop a simple, extensable, generic high speed re-programmable digital filter.

  • Even I get stuck in FPGA Hell

    Yes, even I get stuck in FPGA Hell from time to time. Here's a quick discussion of three problems where I got stuck recently: HDMI input, getting the debugging bus up and running, and an arbitrary clock rate generator. In each case, I present not only how I was stuck, but also how I got unstuck.

  • Glad I went to ORCONF

    My thanks go out to the ORCONF team for making this years conference a success!

  • Off to ORCONF-2017!

    This week, I'm off to ORCONF-2017 in Hebden Bridge, England. I'll be giving a presentation on AutoFPGA, and a quick update on the ZipCPU development.

  • Reinventing PWM

    A PWM output can often be used as a poor man's low-frequency digital to analog converter. Such outputs are so easy to create, that they often make sample problems for beginners. Here, we'll not only show an example of the beginners solution, but we'll also create a simple no-cost improvement that can be applied for audio signals.

  • Big Money Engineering Integrity

    This article is a true story of what happens when engineering integrity is lost at the big money government level. The result wasn't pretty.

  • CORDIC part two: rectangular to polar conversion

    The CORDIC algorithm we discussed can be used in more than one fashion. We've now discussed how to use it to calculate sine and cosine functions. Today, let turn the algorithm around and use the same method to generate polar coordinates from rectangular inputs--essentially the reverss of the last operation.

  • Using a CORDIC to calculate sines and cosines in an FPGA

    Having presented several simple means of calculating a sinewaves within an FPGA, we turn to a more powerful method today: the Coordinate Rotation Digital Computer, or CORDIC. Although this method has a higher latency than the two table based lookup methods, it also has the capability for much greater precision than either table method can provide.

  • Building a quarter sine-wave lookup table

    Since we've already discussed how to build a simple sine wave lookup table, as well as several general strategies for controlling pipeline logic, let's take a look at creating a sine wave from a quarter wave table. We'll also use this as an opportunity to discuss how to create pipelined logic in general.

  • Debugging your soft-core CPU within an FPGA

    We've already looked at the requirements for debugging a CPU in general, as well as how to debug a CPU in simulation. Let's now take a look at how to modify your soft-core CPU so that you can debug it when it is on an FPGA.

  • The ZipCPU's pipeline logic

    Having discussed several strategies for pipelining in general, we turn our attention to the strategy used for handling pipelining within the ZipCPU. Hence, we present the pipelining logic used by the ZipCPU, as well as the variable names you can search on in case you want to see in detail how a CPU can handle its pipeline logic.

  • Rules for new FPGA designers

    This year many students will try to take up digital design. Some of these students will enjoy their experience, many will not. Here's some tips to help keep you out of trouble, so your experience will be one of the more enjoyable ones.

  • Two of the Simplest Digital filters

    The simplest digital FIR filter out there is a simple adjacent sample averager. Here we present not only that filter, but also discuss how any Digital filter may be tested and proven.

  • Strategies for pipelining logic

    Pipelining logic is one of the most basic digital logic concepts. Many processing algorithms can naturally be pipelined--reducing logic and speeding up algorithm completion. However, most pipelines require some form of handshake signals. This post, therefore, discusses those handshaking signals, presenting several options that can be used depending upon the circumstances.

  • What would cause you to lie?

    Engineering integrity should not need to be discussed on any engineering forum. The honesty of every engineer should be assumed. That this is not the case, and that this needs to be discussed is unfortunate. It is, however reality. So, let's ask, what would it take for you to compromise your integrity?

  • A Simple ALU, drawn from the ZipCPU

    When it comes to building a CPU, an ALU may be the simplest part. This discussion examines how simple an ALU can be made to be, by examining the ALU within the ZipCPU.

  • Series: Debouncing in Digital Logic

    This completes our series on button bouncing, and the logic necessary to both measure and to eliminate button bouncing.

  • Using a debug-bus to Measure Bouncing

    While many other FPGA web sites discuss contact bounce and how to get rid of it, let's take a different approach here. Let's combine our debouncer with our measurement code, connect it to our debugging bus, a get a trace from within the FPGA indicating what was taking place.

  • Measuring Contact Bounce

    Now that we know that buttons don't behave like we would like, what would it take to measure that behavior? Let's measure not only the number of times a button changes, but also how long it takes from the initial change to the final change.

  • How to eliminate button bounces with digital logic

    Unilke LEDs, pushbuttons have a series of problems associated with them that make them difficult to use as part of debugging a design. They can be useful, but only after your debouncing logic has first been proven

  • Visualizing Contact Bounce

    Buttons when pressed often report more than one contact, or even more than one release. This post presents the result of measuring several such bounces.

  • ZipCPU Advertising

    Disqus support has been removed, since their advertising was not consistent with my strong Christian scruples. The ZipCPU blog is not, nor has it ever been, supported by advertising.

  • Writing your own VCD File

    If you ever decide you want to create your own scope, but not your own viewer, than knowing how to write a Value-Change Dump (VCD) file may be required. Here, we'll go over the basics of how to write such a file, as well as discuss the meanings of the most common parts of one.

  • Linear Interpolation

    An Overview of the Linear Interpolation Series

  • Getting the basic FIFO right

    A FIFO is a very basic component of any digital logic system. Getting the components and the timing right, though, can be a careful chore. Here, let's examine how to build a basic FIFO.

  • Windows FPGA designers may not need a Linux machine ... yet

    Many of the programs I use for FPGA design and debugging, such as verilator or GTKWave, run just fine under Windows when using Cygwin. Here's how to set up some Linux FPGA tools under Windows.

  • How to build a simulation based debugger for your own soft-core CPU

    While Verilator makes for a great simulator, gtkwave isn't the most intuitive way to debug a CPU. Rather than staring at incomprehensible wires, give your simulator the feel of a proper debugger using these techniques

  • How to Debug a DSP algorithm

    DSP algorithms are not like other algorithms when it comes to debugging. printf() and gtkwave just don't work as well. Let's look into an alternative.

  • Rounding Numbers without Adding a Bias

    If every operation adds to the number of bits required to represent the result, how do you get rid of bits? It's not nearly as simple as it sounds, since most of the methods for getting rid of bits bias the result one way or another. Here we'll examine a couple rounding methods, and discuss their problems, and also describe a solution.

  • Bit growth in FPGA arithmetic

    Integer arithmetic from a small domain, creates larger and larger numbers. Here, we'll quantify that effect.

  • A Basic Upsampling Linear Interpolator

    This blog article is the second in a series on rate conversion within DSP's. Specifically, we'll look at how to upsample an incoming signal from whatever rate it was given to you at, on up to any rate at or less than your FPGA's clock rate.

  • Verilator doesn't find everything (today)

    After posting the debugging bus stories, I was embarrassed to implement it on my own FPGA and not get immediate and perfect success. Verilator just doesn't find everything (today).

  • Design Needs when Debugging a SoftCore CPU

    There's more to designing a CPU than picking the instructions that the CPU must support. This blog post discusses the debugging facilities you are likely to want while you work to bring your design to fruition.

  • The simplest sine wave generator within an FPGA

    If you find yourself needing a sine wave within an FPGA, here's the simplest method(s) I know of creating one.

  • Getting Started with the Wishbone Scope

    This post describes how to get started with the wishbone scope in your own design. As a fun end result, we'll draw the information necessary to create a VCD file and thus a GTKWave plot from logic within your design

  • Finishing off the debugging bus: building a software interface

    This post completes the sequence on what it takes to build a debugging bus, by building a software controller to encode commands for and decode responses from the FPGA. Once built and integrated into your design, the dbgbus controller should be able to help you communicate with components within your FPGA

  • Why you want a debug port into your FPGA

    Just a quick picture of what you can do with the dbgbus once finished

  • Simulating an FPGA through the debugging interface

    Given the debugging interface just created, this post goes into how to go about simulating it via Verilator

  • My own FPGA debugging philosophy

    Many individuals have read my previous posts and have wondered what my design philosophy actually is. This post attempts to outline the general approaches I used to debugging my own FPGA designs

  • Building a very simple wishbone interconnect

    Having now built all of the components of a UART to wishbone bridge, it's time to build a test design that would use it. This article, therefore, discusses how to build the interconnect that will connect a single wishbone master to multiple wishbone slaves

  • Taking a New Look at Verilator

    Verilator is not a simulator in the sense of any of the other commercial HDL simulators on the market, yet it has some very unique capabilities when it comes to simulating components that you won't find in other simulation tools

  • Putting our Debugging Bus RTL Components Together

    We've now built all the individual components of an RTL based debugging bus. This post discusses how to put them all together.

  • Sending bus idle notifications down the line

    One difficult part of dealing with multiple serial interfaces is knowing which one has what port on it. We'll solve this problem on our FPGA debugging interface by adding a simple idle indication into our debugging port. With this capability, if we watch long enough, we can tell if the port is the right port or not.

  • Why Use a Network Interface to your FPGA

    Several of you have asked why the debug interface needs to be networked. What does that mean? and, is it worth the pain of a capability I don't think I need? This article discusses what it takes to network a debugging interface, therefore, and outlines why it isn't as difficult to do as it might sound.

  • Support me on Patreon

    The ZipCPU blog now has Patreon support! If you'd like to see this blog continue ...

  • The debugging bus: a goal for FPGA interaction

    We're now halfway through describing how to build a debugging bus within an FPGA for command, control, and feedback from that FPGA. This post takes a quick review of why we wish to do this.

  • Adding interrupt reporting to our debugging bus

    Now that we have a mostly working bus, let's add interrupt reporting as a simple feature to it

  • How to send our bus results back out the serial port

    We're close to having a working demonstration debug port to our design, but not quite there yet. This lesson focuses on how to turn the output words from our hexadecimal bus back into characters that we can then read on the output.

  • No PI for you

    Neither the units of degrees nor Radians make sense within an FPGA. This article discusses a better unit for angles within an FPGA.

  • How to create bus command words, from a 7-bit data stream

    Continuing our series on how to make a debugging bus, this article discusses how you can create bus command words from a stream of printable bytes.

  • Minimizing FPGA Resource Utilization

    At some time, every project will come face to face with the fact that FPGA resources equal dollars. Keep your dollar commitment small. Use the techniques in this post to keep your resource usage to a minimum.

  • A College Student's Response to the FPGA Design Process

    When I wrote the blog article about the FPGA design process, and how it differed between students, experts, and reality, one particular student's experiences were fresh in my mind. Here, he writes about his experiences from his own perspective.

  • Building a Simple Wishbone Master

    A discussion of how to build a simple bus master, such as you might wish to use to debug a wishbone-based system

  • Building A Simple In-Circuit Logic Analyzer

    Building your own in-circuit logic analyzer is a whole lot easier than it sounds

  • Nearest Neighbor Interpolation

    A simple presentation of how to handle resampling via a nearest-neightbor interpolation scheme.

  • An Overview of a Wishbone-UART Bridge

    I'd like to describe how to control a wishbone bus from an external command and control port. It's not that simple. This article discusses instead how one such approach works, decomposing the parts and pieces of it. It then outlines what a simplified control port structure might look like.

  • Campus Sidewalks and FPGA Design

    Sometimes you need to build something to fill a gap, before you know what to build. Here's an example.

  • Controlling Timing within an FPGA

    Every FPGA design needs to carefully control the timing of events. Here, we'll explore several ways to control timing within your design.

  • The Actual FPGA Design Process

    There seems to be a disconnect between the FPGA design process used by experts, and the students who request help from the online forums. This post examines that disconnect, pointing out the detail that's often missed.

  • Building a simple wishbone slave

    Bus slave interaction is actually fairly easy. Let's walk through an example wishbone bus slave and look at how it works.

  • Bus Select Lines

    If you want 8-bit access to a 32-bit bus, you'll need to incorporate the bus select lines into your logic. See how it's done here.

  • FFT debugging

    If you find you need to debug an FFT and that you are struggling to do so, the answer is that you need to go back to the basics of engineering. Working from the basics, debugging either an FFT or any other block will become straight-forward.

  • Debugging an FPGA through the serial port--first steps

    If you have a serial port, how might you use it to get information from your FPGA? Can you use it to help debug the rest of your design?

  • That first serial port: Debugging when you are blind

    A serial port can be a very useful way to get information from an FPGA. How can you avoid FPGA Hell when you are trying to get that first serial port up and running?

  • Building a simple bus

    For this article, we'll discuss the logic necessary to implement a very simple bus slave.

  • Moving to memory

    Blinking LEDs is a fun exercise, but eventually you will need to learn to walk to grow up. Within FPGA's, that means you'll need to learn how to deal with memory.

  • A Vision for Controlling FPGA Logic

    My approach to controlling and debugging an FPGA seems to be unique among those I share it with. Here I describe that approach for you, as a vision for where we might go here.

  • Which comes first: the CPU or the peripherals?

    Not whether or not the chicken or the egg came first, but in digital design which comes first: the CPU or the peripherals?

  • Knight Rider

    Knight Rider's car: KIT's LEDs can be a fun twist on a beginners first FPGA design

  • FPGA Hell

    FPGA Hell is where your design doesn't work, and you don't know why not. Here, we'll discuss basic approaches to avoiding FPGA Hell.

  • Blinky

    Your first FPGA design -- blinking an LED

  • Most common Digilent FPGA support requests

    After watching Digilent forum support requests for a year, they start to repeat into these categories

  • Cannot be done

    Never underestimate someone's creativity to make things work outside of spec

  • Welcome to the ZipCPU blog!

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