Welcome to Gisselquist Technology’s ZipCPU website!

The web site has been put together to describe, and highlight, some of my experiences both mentoring college students on Digilent’s Forums, as well as when building my own CPU: the ZipCPU. The site is dedicated to keeping FPGA designers from getting stuck in FPGA Hell, a term I use to describe the situation where the FPGA isn’t working and the designer cannot tell why.

I’ve got a lot of things I’d like to teach/blog about. You can read about many of these topics here, and my first welcome post here. The topics I expect to focus on include:

  • The engineering design process [1], and why and how student’s tend to get stuck [2]

  • How to debug logic within an FPGA design, and (if we get the chance) how to debug a CPU within an FPGA.

    o Using Verilator as a simulation tool for not only unit testing, but also for integration testing

    o Learning how to extract debugging information from within an FPGA design running on its hardware, so you can tell what is going on within it

  • Student mistakes and experiences, and how to avoid making the same design mistakes that others get stuck on.

The web site is named after the ZipCPU, a soft core CPU of my own creation, designed to be a fully functional CPU, while using as few FPGA resources as possible. You can read more about the ZipCPU here.

I am an independent consultant and developer, working for Gisselquist Technology, LLC. Gisselquist Technology, LLC is a small, one-man, Christian company providing DSP and digital design services. You can read more about Gisselquist Technology here.