2020 and 2021 in review
In the spirit of looking back at the last year with every new year, shall we take a look back at 2021? No, let’s do better. Last year, we never looked back at 2020, so today let’s look back at both 2020 and 2021. To do that, let’s look up which articles have had the most page views, and then take a look at what articles may be coming up in 2022.
But first, how’s the blog going?
What’s going on with the blog?
Well, first off, the blog is working.
“Working”? What do I mean by that?
Well, as you may remember, my goal with this blog has always been to attract customers to Gisselquist Technology, LLC. I’m a small shop, so I don’t need more than a small handful of customers with just a couple of projects to keep me fully employed. Those who’ve wished to hire me haven’t had a problem finding my (not so well-hidden) E-Mail and writing me directly for support.
So far, it’s worked. I’ve been well employed. Perhaps even over employed, having more tasks than people to work on them. Economically, this is a good place to be in.
Second, the blog itself is no longer funded by a large sponsor. That’s not a big deal, until you realize that the time I put into the blog is no longer funded. It hasn’t made it into my work week this last year. Instead, I’ve kept the blog running on weekend or vacation hours this last year. The sad part of this is that the number of articles I’ve posted has gone down over the years.
- 31 non-quiz posts in 2019
- 25 non-quiz posts in 2020
- 17 non-quiz posts in 2021
The problem I’m having, however, is that I have more work than resources. Keep your eyes and ears peeled on this one. You may discover that there’s more than one of me by the end of the year. We’ll see where the Lord leads between now and then.
Top Posts from 2020
Before diving into the top ten posts from 2020, I should explain why this list wasn’t posted last year at the new year. The reason is simply that the last month of 2020 was dominated by comments made by individuals who wished to cancel the ZipCPU blog for statements I had made that they disagreed with.
Specifically, I had commented that: “God made man “male and female” by design. This is obvious and evident from the creation itself: Only women can give birth. Only women menstruate. Only women suffer from miscarriages. Men who dress like women, who call themselves women, are nothing more than that: men who dress like women, and who imagine themselves to be women. Some may have even made themselves eunuchs. They have not made themselves into women.” This was then my justification for refusing to use female pronouns for a man. You can read more of how this became a business issue in the article, should you be interested. It’s a sad story.
Needless to say, these comments caused quite an uproar on social media.
Despite the uproar caused by these comments, I see no reason to update, correct, or change my comments above. Of all those who have challenged these comments, no one has challenged the truth of their content. The closest anyone has come to challenging the truth of these statements has been based on a “straw man argument”: This person asked me if, by my measure, a woman who could not bear children was no longer a woman. Since that wasn’t what I had said, I see no reason to change or apologize for these comments.
Instead, let me say that if these words offend you, then perhaps this blog isn’t for you. If you wish to stick around, then know that there is a second half to the Gospel of Jesus, the Christ.
Because the end of the 2020 was dominated by the many who were offended, I held off on sharing the top ten articles I had posted in 2020. The following Bible verses share some of my reasons for this: , , 
It’s now been a year and the furor has died down. Those who are offended by these comments no longer read the blog. Indeed, I can even measure the effect. As a result of those who were offended by these comments, I lost about 200 twitter followers out of 4,200, or about 5%. This particular incident hasn’t really hurt me or the blog very much. Indeed, I’m moving on–although I may yet come back and address this issue again if need be.
With that as background, let’s go back and take a look at the top ten articles from 2020 and give them the highlight they deserve based upon their total page views across both 2020 and 2021. Here are these top ten articles from 2020, from least to most popular:
Lessons in Hardware Reuse, 1,590 page views
This is a fun article discussing reuse from a personal, business, perspective. I own all my IP, so I should be able to re-use it without a problem, no? Sadly, what should be a reuse panacea has had some pitfalls within it that I never expected. These surprises are discussed in this article.
This article gets a duckduckgo.com score of #1. It is the top or first hit, when searching duckduckgo.com for “hardware reuse.”
- It doesn’t really seem right to list a post about posts as a top article, but the article, “2019: AXI Meets Formal Verification”, my last end of year summary from two years ago now, received more page views at 1,873 than the Reuse article above.
Moving values and strobes cross clock domains, 2,154 page views
This is one of several clock domain crossing articles that have been a real hit. The first one, Some Simple Clock-Domain Crossing Solutions, discusses CDCs in general. Indeed, this article is a hit in its own right as you’ll see below. This article also discussed how to move multi-bit values across clock domains while keeping them coherent. Once I got heavily involved in formal methods, though, I wanted to start adding formal methods checks to asynchronuos logic. I started, therefore, with a simple article on Formally Verifying an Asynchronous Reset. This didn’t seem complete enough, so I tried another: Formally Verifying Asynchronous Components. This went over the formal verification of a clock switch. A fun project. With these few under my belt, I posted about Crossing clock domains with an Asynchronous FIFO–another big hit as you’ll see below. That’s about as good as you can get, no?
Well, not quite. There’s always a reason to want to transfer values, not data, across clock domains. The difference being that these values don’t necessarily need to move at high speed, and there’s not necessarily another one following the first. It’s just that: a value that needs to cross clock domains.
That’s the focus of the article, but with one other twist: the approach is twice as fast as the one I presented in my first CDC article. Feel free to check it out.
This item gets a duckduckgo.com score of #1, the top/first hit, when searching for “cross clock domain values”.
Re: What does your design flow look like? 2,156 page views
This follows from a question I was handed regarding which tools I use. Since writing the article, I’ve now done a lot more with iverilog and even XCellium (a commercial simulator). Perhaps I may come back and discuss the main differences between these simulation approaches and my preferred approach: Verilator.
While I tried, I was unable to get a valid duckduckgo.com score for this article.
Building a Downsampling Filter, 2,226 page views
This continues our series into filter design and implementation. You can find more DSP articles on the DSP page, if you are interested, to include other filtering articles in this series.
This item gets a duckduckgo.com score of #1, the top/first hit, when searching for “verilog downsampling filter”.
The hard part of building a bursting AXI Master, 3,632 page views
What I’d really like to blog about is how to build one of these bursting AXI masters. I’m not really sure how to get from here to there though. AXI-lite masters are fairly easy to build and verify. AXI4 bursting masters? Those that issue burst requests? Much harder. This article discusses why, and some of the challenges I’ve had while trying to build and verify such masters.
Basically, the formal tool tends to get about 5-10 clock cycles into any bursting master implementation before it starts finding bugs. These are usually associated with issuing the very first burst request of the bus. I then find myself spending a day or even two finding and fixing bugs at this point. It’s just a real challenge to get right. (No, Xilinx didn’t get their DMA right here either–it dies quickly at this point due to a detail I doubt anyone would notice.)
In all, verifying a bursting AXI master can take 3-4 days of work. I’m not yet certain how to turn that into an article that would explain to all how to do it. Until then, this article is perhaps the best I have. It attempts to go over the pitfalls, explain why these masters are a challenge to build, and then to outline what I’ve done to get around the various challenges involved.
Not knowing a good search term, I not going to give this item a duckduckgo.com score.
Is it possible to make a living as a solo digital design engineer? 3,995 page views
This is the article that started the furor mentioned above.
Yes, I can get anxious about where my next paycheck will come from. Yes, as a solo engineer, I worry about where the next job will come from. There are just too many things that I cannot control about my future.
Bottom line: As a business man, I depend upon “gifts” from the Almighty. Such “gifts” often come in the form of contracts. Some come in the form of new business contacts. It’s for this reason that I judge it more important to please God than to please men. Therefore, don’t ask me to lie or otherwise violate my faith. I’d rather find another customer, than to work with someone that requires that I lie.
This item gets a duckduckgo.com score of #1, the top/first hit, when searching for “solo digital design engineer”. This is probably due more to the attention a small section generated rather than the entirety of the article, but so be it. [Ref]
Debugging AXI Streams, 6,166 page views
How shall an AXI stream be debugged? This article presents a fun approach: Use an AXI-lite slave to feed and recover the AXI stream. It’s a simple enough approach. It’s also one of my first AXI stream articles.
This item gets a duckduckgo.com score of #1, the top/first hit, when searching for “axi stream debug”.
The Faith of a Mustard Seed, 8,357 page views
Not all of my blog articles are about digital design. I chose, early on, to also discuss faith and ethics but at a less frequent level. This has kept the ZipCPU blog and twitter feed from being aggregated with other tech blogs that don’t have this “feature”.
This article, regarding the faith of a mustard seed, presents a missing viewpoint on Jesus’ teachings of mustard seeds. It’s a completely different take from the mainstream. It turns Jesus teaching from an impossibility into an encouragement.
I’m honored that so many individuals have enjoyed this article.
Perhaps I shouldn’t be surprised, but this article only gets a duckduckgo.com score of #89 when searching for “faith of a mustard seed”. Sadly, most of the prior articles describe this faith as the least of all faiths, since the size of the mustard seed is so small. I argue in the article that this is entirely the wrong way to understand the parable, but you may have to read it to know more.
Building an AXI-Lite slave the easy way, 9,610 page views
When I first built my formal AXI-lite properties, I tested them on Xilinx’s demonstration design. (They call it their AXI-lite “template.”) I was surprised to find it horribly broken. Once you have a set of formal properties, though, it becomes really easy to build your own design that meets those properties. That became the basis for my next post on the topic of AXI-Lite.
The problem was that this first version of an AXI-Lite slave wasn’t very easy to work with.
Over time, as I got to working with AXI-Lite, I sort of settled on a simpler skeleton design to start from. I call it my “easyaxil” design. This is the design I go to when I need a control port for any new interface. It’s simple, and easy to work with. This article presents that simpler design.
This item gets a duckduckgo.com score of #1, the top/first hit, when searching for “axi-lite slave”.
Building a basic AXI Master, 12,219 page views
This is the first post I’ve written regarding building an AXI master. I’ve since written others, but this remains a good, basic, startup guide for building an AXI master. Not only does it outline the basic templates for the required AXI logic, but it also discusses the context in which an AXI master will find itself, and a taxonomy of the various types of AXI masters.
The only drawback to this article is that the AXI master presented is really a bridge. Rather than some ethereal “AXI master”, this one bridges from Wishbone to AXI. Not everyone uses Wishbone. In hindsight, perhaps that’s not so bad: any bus master needs to accept its direction from somewhere. 1) Both CPU fetch and memory units need to get their direction from the CPU. 2) A DMA needs to get its direction from a control port. 3) My debugging bus master gets its direction from a character stream. Why should getting direction from a Wishbone slave interface be a problem?
Perhaps the only problem here is in the imagination of the reader, since all of the principles are the same.
The one thing this article doesn’t discuss is how to build an AXI master that will generate burst requests. I’ve discussed some of the problems with presenting such a burst request generating master above. On the other hand, if you don’t need burst requests, this might just be ideal.
This item gets a duckduckgo.com score of #1, the top/first hit, when searching for “axi master”.
Top Posts from 2021
Let’s now turn our attention to the top ten posts, posted in 2021, as sorted based upon their number of page views. Since these articles are being judged based upon a year, or less, they will (obviously) have fewer page views than those of 2020 above.
Building a Better Verilog Multiply for the ZipCPU, 980 page views
Many articles have been written about how to build a digital logic multiply. Many of these focus on Wallace trees and some other amazing implementations. The reality is, though, that knowing how to build a blazing fast multiplication algorithm on an FPGA is often irrelevant: FPGAs have hardware multiplies you can use for that purpose. Why slow down your clock to create one of these faster multiplies?
On the other hand, what if your goal is ultra-low logic, and you are working on a device either with no hardware multiplies to work with, or perhaps no hardware multiplies left? This article focuses on just that situation within the ZipCPU, and the resulting algorithm saves a lot of logic in the end.
This item gets a duckduckgo.com score of #2 when searching for “Verilog multiply”.
Examples of AXI4 bus masters, 1,017 page views
I’ve discussed above the struggles I’ve had trying to describe how to build complex AXI masters on the blog. The topic just doesn’t fit in a blog article very well. This article, on the other hand, goes over a list of examples of such masters. Perhaps, if you need to build your own AXI master, you might find an example to suit your purpose from among the many listed?
This item gets a duckduckgo.com score of #2 when searching for “AXI master example”. Sadly, the first hit is for a Xilinx HLS support request, from someone who was not able to get a working AXI4 master under HLS. It’s somewhat of a shame, since Xilinx’s AXI4 master template does work–under the right conditions.
AXI Handshaking Rules, 1,030 page views
I’m often surprised by the number of help requests on Xilinx’s forums, from people trying to get a custom AXI-whatever to work, but who can’t get the basic AXI handshake right! This is one of those fundamental things. You are not going to get AXI-anything to work if you mess up the handshaking.
Indeed, I would strongly recommend that you learn the rules of the AXI handshake before you write online asking for help. That’s the background of this article. Indeed, there are some basic template logic blocks offered in this article which, if you follow them, will guarantee that you get the handshake right. It’s not that hard to do, and I end up naturally using those logic templates over and over again. As a result, this is a good article to read when you are having AXI problems–before you go about embarrassing yourself.
This item gets a duckduckgo.com score of #1, the top/first hit, when searching for “axi handshake”.
Clock Gating, 1,067 page views
Clock gating on an FPGA is great when you want to emulate an ASIC design. You’ll need special vendor primitives to do it.
That’s not the topic of this article.
This article is instead about whether or not gating a clock would improve simulation performance. At first, it looked like the answer would be a resounding yes. So, I implemented a bunch of clock gates and then measured everything. In the end, it didn’t appear to improve Verilator performance by any significant amount, but the experiment was pretty fun and I learned a lot from it. As a bonus, the ZipCPU can now shut down its clock when it’s either shut down or waiting for an interrupt. Cool, no?
This item gets a duckduckgo.com score of #5 when searching for “clock gating”.
Measuring AXI latency and throughput performance, 1,188 page views
Being able to know how well your AXI bus is running is a big deal. Where are your clock cycles going? How fast are requests being made? How long does it take them to get from the processor to your slave? Measurements are always the first steps in any bus performance optimization effort.
The problem is that AXI is … complicated. It’s even worse in an environment containing burst requests, multiple IDs, multiple masters, and multiple slaves. This article, therefore, attempts to distill the relevant information from the AXI bus in order to create simplified AXI performance measures you can use to know how fast your design is (or isn’t) running.
This one is pretty valuable. The logic for the performance monitor is posted. Feel free to try it out.
In this case, the Verilog AXI performance monitor, presented in this article, gets a duckduckgo.com score of #5 when searching for “AXI performance measurement”. The article itself, however, doesn’t come up in the top 100.
Building a Simple AXI-lite Memory Controller, 1,264 page views
Let’s now return to our ZipCPU roots, and see what it takes to build a CPU memory controller that speaks AXI. In this case, it’s about building an AXI-lite memory controller, although a later article (that didn’t make the top-ten) will convert this AXI-lite memory controller to a full AXI memory controller–complete with exclusive access and data width trimming.
Still, this article forms the basis for one of the AXI masters I test the AXI performance monitor with.
This item gets a duckduckgo.com score of #1, the top/first hit, when searching for “axi-lite memory controller”.
Fixing Xilinx’s Broken AXI-lite design in VHDL, 1,358 page views
I don’t normally do VHDL. Sorry, but Verilog has now been my home since about 2007 or so. However, I currently have a copy of SymbiYosys that can be used to verify VHDL designs, so why not try it out? In this case, I used Vivado to generate an AXI-lite design, and then ran SymbiYosys on it. After verifying that the basic Xilinx AXI-lite bugs were present, I then updated the design until it passed a formal check. Yes, there are only a small number of updates required to get the design working, and I even get it working well, but for some reason this post has been well loved in spite of the minimal amount of work involved.
How well does the design work in the end? Well, without a skid buffer, the best you can do is 50% throughput and this design doesn’t use a skid buffer. Still, the updated design hits 50% throughput number even though Xilinx’s original write performance was 33% at best. Indeed, once you either know what you are doing, or rather once you can pretend with a formal tool and an AXI-lite property set, then getting your performance up there isn’t all that hard.
This item gets a duckduckgo.com score of #1, the top/first hit, when searching for “axi-lite VHDL”.
Common AXI Themes on Xilinx’s Forum, 1,935 page views
Once I thought I knew how to verify AXI designs, I started examining Xilinx’s forums looking for designs to verify. Indeed, I think I went so far as to look for any forum request with the word “AXI” in its title.
The fun result is that I got quite the survey of problems individuals were struggling with when using AXI. The post, therefore, is very informative. It’ll tell you a lot about how others, both new and experienced, view AXI and Xilinx’s AXI IP.
There is a problem, however. Since posting this article Xilinx has completely revamped their community forums. As a result, all my links to the original forum posts are now lost. I haven’t (yet) had the opportunity to try to go back and look up the new links (Xilinx promises that they can be found by searching for them anew), and Xilinx hasn’t shown any interest in fixing these broken links. So, while the article is really cool, the references it depends upon will take some work to look up.
This item gets a duckduckgo.com score of #1, the top/first hit, when searching for “xilinx forum themes”, and the #3 hit when searching for “xilinx forum axi”.
Lessons learned while building an ASIC design, 2,177 page views
My first ASIC design! I was surprised at the many things I learned along the way. Things like, logic is cheap but verification is expensive. Or, you can’t go back and put features into a design later, they have to been in when you turn the design in. Or, much to my surprise, the moment you start you are late.
Still, there was a lot to learn, and this article is the #2 article from 2021.
This item gets a duckduckgo.com score of #5 when searching for “asic lessons”. It might’ve been higher, but three articles regarding the “Australian Securities and Investments Commission” ended up getting placed higher.
The FPGA designer who didn’t get the job, 6,870 page views
This article follows the following conversation:
Friend: Can you provide someone with some work? I’m thinking of hiring him, and would like to give him some work in order to evaluate his capabilities.
Me: Well, I have a design that hasn’t yet been tested. Why not have him run it through it’s paces, and see how well it works? This will show us his simulation capabilities, his Verilog capabilities, and even better any formal background he might have.
Potential hiree: Sorry, I want a design job, not a verification job.
I spent one round trying to convince him that he was being evaluated for a design job, and that a design engineer needs to know how to verify his own stuff–especially when working for a small company.
In the end, this engineer didn’t get the job. I might argue he was too proud to lower himself to working with someone else’s designs. Others have argued that I was the problem in the whole affair. Perhaps. I’ll let you read the article and decide for yourself.
Of all the articles written in 2021, this one had more views than any other.
I searched duckduckgo.com for “fpga design job”, but this article was so far buried behind job postings that I don’t have a score for it.
Top 10 Posts across all of 2020 and 2021
In many ways, I haven’t really figured out the right “top articles” metric to use at the end of the year for this review. Should the “top articles of 2021” be from the articles written in 2021, or should it be from all of the articles read in 2021? To make matters a touch worse, the top ten articles written in 2021 tends to be biased towards articles written earlier in the year, which have had time to accumulate more page views. The end result is an indecision that has lead me to post multiple lists instead just a single one. Therefore, here’s the list of the top ten articles read in 2020-2021, regardless of the year they were written within.
Building a basic AXI Master, 12,219 page views
This was one of the 2020 articles we discussed above, but it’s made it into the overall top ten, so I’ll list it again here.
As mentioned above, this item gets a duckduckgo.com score of #1, the top/first hit, when searching for “axi master”.
Building a high speed Finite Impulse Response (FIR) Digital Filter, 13,090 page views
I’ve come back to filtering several times over since, but this was one of my earlier filtering articles. It seems quite well loved.
This item gets a duckduckgo.com score of #5, when searching for “fast verilog fir filter”. “Fast” in this case is necessary to separate this filter’s implementation from other, perhaps more common, “slow” filter designs.
FPGA Hell, 13,858 page views
This isn’t really a regular article, so I’m not going to rank it among the top ten articles of 2020-2021. It does get a large number of page views, though, so I figure I should list it here anyway.
This item gets a duckduckgo.com score of #1, the top/first hit, when searching for “fpga hell”. Perhaps that’s too much of a give me, but that just seems the most appropriate search term for this article.
Building a Simple Logic PLL, 13,960 page views
I’m not sure if those who find this article realize that it’s presenting a logic PLL, rather than a more traditional analog PLL. It’s not any less important, though. I’ve used this algorithm many times over, for many purposes. Indeed, it now exists in an ASIC–but that’s another story. This year, this articles comes in at #8.
This item gets a duckduckgo.com score of #4, when searching for “Verilog PLL”.
Gisselquist Technology Projects, 14,141 page views.
Well, I guess folks want to know what I’m up to.
This page doesn’t really have any of my commercial projects on it. Instead, it’s focused mostly on my open source projects. That’s okay, but perhaps I should coordinate adding some commercial projects here. I mean, I’ve been doing some really cool ASIC and SONAR stuff, both of which might be fun to list.
Formal page, 14,516 page views
As with the last page, this isn’t really an article and so I’m not numbering it among the top ten articles in 2020-2021, even though the number of page views this page has received would properly place it there.
This formal page is simply an index of formal verification articles. For those who are interested in formal as an end, you might find this page valuable. For those interested in anything that uses formal, you might wish to keep an eye on the blog–since I often discuss how to verify various types of logic outside of the links in the formal page.
Taking a New Look at Verilator, 14,612 page views
This is my favorite Verilator article, although I haven’t revisited it in some time. The principles have remained much the same. The biggest thing that’s changed for me and my usage of Verilator has been where to find various Verilator internal values that … I probably shouldn’t be peeking at anyway. I still use Verilator for almost all of my simulation needs, and this article remains a good introduction to how I do it.
This item gets a duckduckgo.com score of #18, when searching for “Verilator”.
Using a CORDIC to calculate sines and cosines in an FPGA, 14,845 page views
I used to think that CORDICs were the greatest end-all, be-all for FPGAs working with sine waves. You can use them to calculate sine waves of any precision–just add enough rotation rounds. Indeed, my own CORDIC core generator will do just that–and figure out how many rounds are required for any given precision at the same time.
Perhaps that explains why this article is so interesting? It’s the default standard for generating sine and cosine waves within an FPGA.
What’s not said is that CORDICs can be very expensive logically if you want a lot of precision. I first learned this when building a brushless DC motor system designed to run on an iCE40. The CORDICs took the majority of the design. Just because they don’t use multiplies, doesn’t mean they don’t use logic.
Perhaps I might come back to this topic again this year, and present something that works better? What works better? Well, with just one or two multiplies, you can turn a table lookup followed by an interpolator into an awesome sinewave generator that’ll easily best a CORDIC for the least logic required metric–without the scale issues that come with using a CORDIC.
My Verilog CORDIC core generator gets a duckduckgo.com score of #9, when searching for “CORDIC”, whereas this article is #17 under the same search.
Building the perfect AXI4 slave, 15,067 page views
Sadly, it seems there aren’t that many good articles on building full AXI4 slaves. Most of the Google results you get send you to Xilinx’s broken AXI4 design–and that doesn’t really help. I mean, not only is it broken, but it’s not even fully featured. It only handles some addressing modes and some data widths, and under certain conditions … it’ll crash and hang your whole system down with it.
This article provides the “something better” that’s needed, so I can understand how it might be well loved.
The one thing this article doesn’t discuss is exclusive access, and specifically how to modify a slave so that it will support exclusive access. I should add that topic to my “To-do” list, since it is a problem I managed to solve this last April (2021).
This item gets a duckduckgo.com score of #1, the top/first hit, when searching for “axi slave”.
Understanding AXI Addressing, 18,251 page views
As you may have gathered from above, Xilinx didn’t get the addressing modes right in their slave template. It’s worse than that: very few AXI slaves properly implement all of the various AXI addressing modes: FIXED, INCR, and WRAP, for all of the various AxSIZEs the slave should be able to support. This is a shame. They’re not that hard to implement. Even better, once you figure out how to handle these addressing modes properly–you’ve figured it out, and you can reuse that address handling logic over and over again.
That’s exactly the purpose of this article: how to calculate the next address in an AXI4 burst regardless of the addressing mode. The result is a module, developed (and even optimized) within the article, that can be then used and reused for this purpose. Indeed, once you have the “next-address in burst” module, the rest is easy.
This item gets a duckduckgo.com score of #1, the top/first hit, when searching for “axi addressing”.
Getting the basic FIFO right, 21,426 page views
This article is well loved. Sadly, it desperately needs to be rewritten. The Verilog FIFO presented within the article is broken. (The C++ software FIFO isn’t …) Since writing this article, I’ve not only rewritten my synchronous Verilog FIFO, but I’ve also added several features to it to make it more hardware independent. Even better, the new/updated synchronous FIFO is formally verified–something missing from the first one, that would’ve caught the errors within it.
An updated FIFO article, therefore, really needs to be on my “To-do” list as well. Until that time, feel free to check out the FIFO lesson in my Verilog tutorial.
Much to my surprise, and perhaps explaining this articles ranking at #3 for all of 2020-2021, it gets a duckduckgo.com score of #9 when searching for “Verilog FIFO”.
Some Simple Clock-Doman Crossing Solutions, 27,077 page views
This article has now held a top spot for several years in a row. It was the #4 article back in 2018, when I wrote my first top-ten articles in 2017 post. It was the #2 article in 2018. It was again the #2 article in 2019, the year AXI met formal.
At this point, my guess is that this will remain a top-ten article for some years to come.
This item gets a duckduckgo.com score of #8 when searching for “Clock domain crossing”.
Crossing clock domains with an Asynchronous FIFO, 27,775 page views
Coming in our number one spot, the top article read in all of 2020 and 2021 is my Asynchronous FIFO article. This article goes over and reviews the Asynchronous FIFO article from Sunburst-Design, and then formally verifies that the Sunburst-Design asynchronous FIFO works–even going so far as the two write test with arbitrary clocks. Perhaps one of the reasons why this article is so well loved is that it actually proves several of the statements made by Sunburst-Design, perhaps it’s just that Asynchronous FIFOs are exceptionally useful, and that a single article may not be sufficient to understand one.
This item gets a duckduckgo.com score of #11 when searching for “Asynchronous FIFO”. Thankfully, the sunburst-design article upon which this Async FIFO article is based comes in at #2.
Verilog Tutorial, 45,454 page views
I’m not going to rank this page together with the top-ten articles listed above, but it is clearly getting the greatest number of page hits among all pages on the ZipCPU blog.
For those not familiar with my tutorial, it’s a bit different in format: I try to teach simulation and formal verification techniques together with design techniques from the very beginning. I also simply Verilog a bit to do this.
For some, this is the greatest Verilog tutorial out there. For others? Not so much. Either way, though, it is free, and it does come with exercises you can do at your desk either with or without hardware.
I have started work on an Intermediate tutorial. The big difference between the beginner’s tutorial and the Intermediate tutorial is that the Intermediate tutorial focuses on bus components: slaves and masters. Unfortunately, this project is moving at a snails pace. This year I’ve only managed to finish up to lesson five of that tutorial. There are many lessons left to be written within it. Worse, I haven’t tested any of the example designs, so … your mileage might vary when trying it out. Still, my current partial work is available for examination if you want to look through it.
Until then, the beginner’s tutorial is really the only complete tutorial I have.
Upcoming Posts to look forward to
I also have several articles in my “hopper”–things I’m working on, but that are still some distance from completion. If you are sponsoring the blog, feel free to write me and let me know if you have a particular interest in one or more of these articles–or even an article on some other topic. Otherwise, here are some of the articles that may (or may not) be completed this upcoming year if the Lord is willing.
Cubic splines, and the Mother Spline
Lots of people think cubic spline interpolation is the end all of interpolation, and if they could just get cubic spline interpolation working on an FPGA they’d have it made.
My current cubic spline (draft) article presents how to generate a cubic spline interpolator for an FPGA. The solution is somewhat unique, in that the data set is assumed to be infinite, and the matrix solution required for the interpolation is done off-line in a data independent fashion. This generates the “Mother Spline” in the title. This “Mother Spline” then makes it possible to implement a cubic spline via a small convolution (FIR) applied to the original data set, followed by a second convolution with a known piecewise cubic polynomial–such as we’ve already discussed on the blog. Even better, because the majority of the spline solution is handled off line, the resulting solution can easily be applied to any infinite data set–such as an ongoing audio or radio frequency source. Sadly, the solution itself is not exact. Perhaps that’s not so bad, though, since the solution can be made arbitrarily close to a true cubic spline by whatever delta your implementation requires. In other words, it’s be good enough for engineering work, although perhaps not good enough for the mathematicians.
I’ve now worked on and off on this article off for months. So far, it’s only slowed down the eventual postings of other articles. I’d still like to finish it, though. The last steps will be to figure out how to explain how to generate the FIR, and then how to implement the necessary piecewise cubic. Once done, this should be a nice contribution to the topic.
RAW SPI Slave
This is a much simpler article than the cubic spline article.
This article is based around an SPI slave implementation that already exists, has already been built, and already passes a formal test. That should make it easier to finish. The key feature of this SPI slave is that it uses the SPI clock for most of its work. Well, why not? One of the big criticisms I received from my article, Rules for new FPGA designers, was my recommendation that everything should use one clock, and the example the critic provided that violated this rule was an SPI slave. He argued that SPI slaves should use the SPI clock for their work. So, I decided to see how hard the task might be.
As it turns out, doing this right is much harder than it looks. Not only that, but I wouldn’t have realized there were any problems were it not for the formal proof. Lord willing, this article, when finished, will clearly outline these pitfalls.
“It’s not my fault!”
One of the sad realities of posting open source designs is that people will try to use them and fail–not because of any problem within the open source design itself, but rather because of a bug within their own design. This seems to be quite common.
This presents a bit of an economic headache for the open source designer, a headache which forms the topic of this article. The problem is that the open source design and its maintenance are “paid for” (somehow), but finding and fixing bugs in user designs that use the open source design are not.
This article tells the story of one such interaction.
Steps to design checkoff
This article focuses on a common tension between engineering and management. When will the design be complete? Management wants a schedule. A typical engineer’s response, however, is “When it’s complete” or perhaps, “I’m working on it.” Both of these are totally unacceptable to management.
Lord willing, this article will present a formal verification based road map to a solution to this problem.
I mentioned above that I need to rewrite my synchronous FIFO article, so here’s a place holder for that rewrite. Lord willing, this rewrite will include such things as how to create a synchronous FIFO from either distributed or block RAM–with the key difference being that block RAM requires a clock to read from memory into a register, such as an iCE40 requires, before the result can be used. I’d also like to discuss building a FIFO where you can write to it when full (and reading), and where you can read from it when empty (and also writing).
In other words, it’d be nice to create a full featured FIFO article.
Sadly, this one needs a lot of work. It’s a long way from completion, so it might take some time to get there.
One of the challenges of digital filter design is how to modify a well designed filter in real time. Often, the big problem of modifying the filter is the FFT implementation the filter lies within. The filter has been tuned so that it can be implemented between an FFT/IFFT pair. Any changes to the filter in this space can cause it to violate the circular convolution properties the filter was built with.
M-Band filters offer a way of getting around this problem, forming the topic of this article.
Some time ago, I reviewed Xilinx’s release of Vivado 2021.1. Specifically, I examined several known “bugs” that had existed in Vivado based IP for years, to see if Xilinx had fixed any of those bugs. Sadly, the review was done on twitter and the graphics necessary to support it are now long gone from the link above.
I’m likely to repeat this review sometime again in 2022, to see what bugs they’ve fixed. Sadly, this means I’m going to have to download another 51GB+, and possibly break several of my own designs (always a risk on any upgrade), so I’m not very eager to do this. We’ll see what happens.
This work will almost certainly wait for Xilinx to fix Vivado’s Y2022 bug. That looks like it’s going to impact a large number of users. We’ll see how they handle it.
For the Software Engineer who wants to build his own soft-core CPU on an FPGA
Yeah, I know, everyone wants to build their own soft-core. It’s a fun project, even though an older hand will often wonder just how many times its worth rebuilding the wheel.
Lord willing, this particular article will offer some encouraging and thought provoking words to anyone in this situation. It’s mostly written, so we’ll see where it goes and whether or not I complete it.
Software vs Hardware, where to draw the line?
This is a topic based on some conversations I’m having locally. It’s been quite thought provoking one for me. A friend is pointing out to me that I’ve now gotten to the point where I’ve started looking at the world like a hammer, viewing every problem as a nail. In my world, that means that every digital logic problem is something to be solved in hardware / Verilog.
The reality is that there needs to be a dividing line, somewhere where it makes more sense to do some things in software and others in hardware. Where is this dividing line? That would be the topic of this article.
AXI4 slave exclusive access
Back in April of this year, I figured out how to modify my AXI property set to handle exclusive access. I learned a lot in the process. I’ve since tested the exclusive access properties on several design components. One in particular, the AXI4 slave I presented on the blog, is easily modified for exclusive access.
Given that there really aren’t any other examples of exclusive access handling that I can find on the web, this might be a unique one once shared. It’s actually worse than that, since many of the AXI interconnects you’ll find on the web break exclusive access–but that’s another story that may, or may not, make it into this article.
Beating CORDIC with just two DSPs
I mentioned above that I have a sine wave generator that requires just two DSP elements. The logic for this generator is posted, although I haven’t mentioned it much on the blog. It’s a curious design, though, in this respect: it’s really easy to generate the table in such a manner that my test bench doesn’t have sufficient capability to verify it. The sine wave distortions simply require an FFT too big than I can implement. The good news is that the two DSP’s used by this algorithm, should your device have them, often render the logic usage much less than a similar CORDIC. Even better, you don’t have the scale issue associated with the CORDIC when using this sine wave implementation.
Not bad, huh?
The algorithm is built around previous article(s) I’ve written on interpolation, so there’s nothing really new here, save the awesomeness of the performance of this technique. Well, a good explanation of what’s going on will probably still go a long ways as well.
I just need to write it up.
While not directly related to the blog, I would like to cut a new release of the ZipCPU this year. The new release speeds up the debugging interface, and adds (optional) clock gating and bus independence with support for both Wishbone, AXI-Lite, and AXI4 buses. Since the debug interface gets fundamentally changed by this release, this will necessitate a major version update. The good news is that the logic for this release is complete. It’s been tested, and it works. The bad news is that the documentation has fallen a touch behind. Updating this documentation, and then releasing a new version will be my next ZipCPU task.
I guess the bottom line is that both the ZipCPU and the ZipCPU blog are alive and well. There’s still future in both of them, and I’m still going. Indeed, Gisselquist Technology is now going stronger than I thought I ever would be–Thanks be to God for His blessings and “gifts”.
And saying, Where is the promise of his coming? for since the fathers fell asleep, all things continue as they were from the beginning of the creation. For this they willingly are ignorant of, that by the word of God the heavens were of old, and the earth standing out of the water and in the water: Whereby the world that then was, being overflowed with water, perished (2Peter 3:4-6)