When I wrote this question, it was supposed to be a fun trick question. All of the answers were intended to be correct.

Unfortunately, I got tricked myself. Specifically, according to the 2012 SystemVerilog standard, the $rose(X) and $fell(X) expressions are dependent upon the LSB of X, whereas $stable(X) and $changed(X) reference the entire bit vector. Worse, this is one of those places where Verilog doesn’t follow the C-standard of anything non-zero is “true” and zero is “false”. No, these two depend upon the LSB of X. Hence, to make these assertions succeed, you need to update them as noted above.

No, I didn’t know this when I wrote the question. A friend thankfully suggested I check the spec, and we both learned during the process.