As noted above, Wishbone permits a response to a request on the same clock cycle that the request is being made. This is different from AXI, for which no combinatorial paths between inputs and outputs are allowed. Therefore, to be consistent with the standard, we need to allow and check for a combinatorial path between request and response.
This explains the assertion above. If there are no outstanding requests and no request is being made and accepted on the current cycle, then the slave is not allowed to acknowledge what would be a non-existent bus request.